From patchwork Tue Apr 3 13:26:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Olivier Matz X-Patchwork-Id: 36946 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7CE781B6D9; Tue, 3 Apr 2018 15:27:01 +0200 (CEST) Received: from proxy.6wind.com (host.76.145.23.62.rev.coltfrance.com [62.23.145.76]) by dpdk.org (Postfix) with ESMTP id 88FB71B69D for ; Tue, 3 Apr 2018 15:26:59 +0200 (CEST) Received: from glumotte.dev.6wind.com. (unknown [10.16.0.195]) by proxy.6wind.com (Postfix) with ESMTP id 3ACB01558AB for ; Tue, 3 Apr 2018 15:25:55 +0200 (CEST) From: Olivier Matz To: dev@dpdk.org Date: Tue, 3 Apr 2018 15:26:44 +0200 Message-Id: <20180403132644.23729-1-olivier.matz@6wind.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170630142609.6180-1-olivier.matz@6wind.com> References: <20170630142609.6180-1-olivier.matz@6wind.com> Subject: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The initial objective of commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting") was to add an empty cache line betwee, the producer and consumer data (on platform with cache line size = 64B), preventing from having them on adjacent cache lines. Following discussion on the mailing list, it appears that this also imposes an alignment constraint that is not required. This patch removes the extra alignment constraint and adds the empty cache lines using padding fields in the structure. The size of rte_ring structure and the offset of the fields remain the same on platforms with cache line size = 64B: rte_ring = 384 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 rte_ring.cons = 256 But it has an impact on platform where cache line size is 128B: rte_ring = 384 -> 768 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 -> 256 rte_ring.cons = 256 -> 512 Link: http://dpdk.org/dev/patchwork/patch/25039/ Suggested-by: Konstantin Ananyev Signed-off-by: Olivier Matz --- doc/guides/rel_notes/deprecation.rst | 6 ------ doc/guides/rel_notes/release_18_05.rst | 8 +++++++- lib/librte_ring/Makefile | 2 +- lib/librte_ring/rte_ring.h | 16 ++++++---------- 4 files changed, 14 insertions(+), 18 deletions(-) diff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst index 40448961a..84e153461 100644 --- a/doc/guides/rel_notes/deprecation.rst +++ b/doc/guides/rel_notes/deprecation.rst @@ -139,9 +139,3 @@ Deprecation Notices required the previous behavior can be configured using existing flow director APIs. There is no ABI/API break. This change will just remove a global configuration setting and require explicit configuration. - -* ring: The alignment constraints on the ring structure will be relaxed - to one cache line instead of two, and an empty cache line padding will - be added between the producer and consumer structures. The size of the - structure and the offset of the fields will remain the same on - platforms with 64B cache line, but will change on other platforms. diff --git a/doc/guides/rel_notes/release_18_05.rst b/doc/guides/rel_notes/release_18_05.rst index 9cc77f893..4d0276f1d 100644 --- a/doc/guides/rel_notes/release_18_05.rst +++ b/doc/guides/rel_notes/release_18_05.rst @@ -86,6 +86,12 @@ ABI Changes Also, make sure to start the actual text at the margin. ========================================================= +* ring: the alignment constraints on the ring structure has been relaxed + to one cache line instead of two, and an empty cache line padding is + added between the producer and consumer structures. The size of the + structure and the offset of the fields remains the same on platforms + with 64B cache line, but changes on other platforms. + Removed Items ------------- @@ -176,7 +182,7 @@ The libraries prepended with a plus sign were incremented in this version. librte_power.so.1 librte_rawdev.so.1 librte_reorder.so.1 - librte_ring.so.1 + + librte_ring.so.2 librte_sched.so.1 librte_security.so.1 librte_table.so.3 diff --git a/lib/librte_ring/Makefile b/lib/librte_ring/Makefile index bde8907d6..21a36770d 100644 --- a/lib/librte_ring/Makefile +++ b/lib/librte_ring/Makefile @@ -11,7 +11,7 @@ LDLIBS += -lrte_eal EXPORT_MAP := rte_ring_version.map -LIBABIVER := 1 +LIBABIVER := 2 # all source are stored in SRCS-y SRCS-$(CONFIG_RTE_LIBRTE_RING) := rte_ring.c diff --git a/lib/librte_ring/rte_ring.h b/lib/librte_ring/rte_ring.h index 253cdc96a..d3d3f7f97 100644 --- a/lib/librte_ring/rte_ring.h +++ b/lib/librte_ring/rte_ring.h @@ -62,14 +62,6 @@ enum rte_ring_queue_behavior { struct rte_memzone; /* forward declaration, so as not to require memzone.h */ -#if RTE_CACHE_LINE_SIZE < 128 -#define PROD_ALIGN (RTE_CACHE_LINE_SIZE * 2) -#define CONS_ALIGN (RTE_CACHE_LINE_SIZE * 2) -#else -#define PROD_ALIGN RTE_CACHE_LINE_SIZE -#define CONS_ALIGN RTE_CACHE_LINE_SIZE -#endif - /* structure to hold a pair of head/tail values and other metadata */ struct rte_ring_headtail { volatile uint32_t head; /**< Prod/consumer head. */ @@ -101,11 +93,15 @@ struct rte_ring { uint32_t mask; /**< Mask (size-1) of ring. */ uint32_t capacity; /**< Usable size of ring */ + char pad0 __rte_cache_aligned; /**< empty cache line */ + /** Ring producer status. */ - struct rte_ring_headtail prod __rte_aligned(PROD_ALIGN); + struct rte_ring_headtail prod __rte_cache_aligned; + char pad1 __rte_cache_aligned; /**< empty cache line */ /** Ring consumer status. */ - struct rte_ring_headtail cons __rte_aligned(CONS_ALIGN); + struct rte_ring_headtail cons __rte_cache_aligned; + char pad2 __rte_cache_aligned; /**< empty cache line */ }; #define RING_F_SP_ENQ 0x0001 /**< The default enqueue is "single-producer". */