From patchwork Tue Jan 23 15:05:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shweta Choudaha X-Patchwork-Id: 34362 X-Patchwork-Delegate: helin.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E04761B170; Tue, 23 Jan 2018 16:05:53 +0100 (CET) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by dpdk.org (Postfix) with ESMTP id 4F9AA1B16D for ; Tue, 23 Jan 2018 16:05:53 +0100 (CET) Received: by mail-wm0-f66.google.com with SMTP id v71so2543004wmv.2 for ; Tue, 23 Jan 2018 07:05:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NpAHV9EE2na0f2m69PjPlFug90U5rxL9O9aPBSWnZdY=; b=QfCbLdWABpBbswMrhN3GqWNyD/RbCyLF4LA8vmdHTrh7ufhygYRXDiNYuZHNVuqqJb HN+EEBmuOvGSEIF4MK2B6nDyKp1lG/jnrL/ca1oTetFCUtwDDBYG6WHasUaIpBeJMjoO /vFShpJIfv0Ycd7zpu1/CPWVaNvrM2cP0IkVDXC70M1MVuIRxiWj6+N6EIZ1dzifNxDs meMmeZMd+ekPzxShPt3WSH1ISQB1P1fOhjA2DC7FkkVzqPtMg4HImtHb8dK4kgnulMht KI0kc7iDXH7V9I530DCjzB3aGx0OmyaDO/8ke0JBnAvOMu7HDyZiWy3llD9UbrL40asT U0ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NpAHV9EE2na0f2m69PjPlFug90U5rxL9O9aPBSWnZdY=; b=VbzwCJkwl6aa9lCWRKiTohtB5oqE66XAdO1UAtIaORrZXa/g4blWd0Lg2wDe0Y+kyL pjXIv/Akx6mHZa0IvIjJ2Dew8m0WJibvvlii5ZQTpn9oxrx6zwm3vYPNePQRFT6A9U5B mxOhdH2tj9CL6hIqpB0gvWOu8JVr0stY+PmI5fTVI/o1dioNkjZ1jz4fC6bYq9qM9120 s5qHzwPbqLvax6K2LAH8olAa6ZOhlpiwLrgFUIPnppsmG12VLkBXHL3RmCjX5VrvuQOz NDPkd/9bGtCA7vK4a6lJ6zUJlsPkeLalmh213W4tNNS252F1PyiIb7rXmmB7xbzEJWI4 INew== X-Gm-Message-State: AKwxytdz474LoazJfK66+t3IBw+nkWPSqgvfaZi2ZsqmKl8YMMiF4714 rn28LzJM3vchGE9Vws5wWxSkcA== X-Google-Smtp-Source: AH8x225DlxQFJue0qDQDpOJvYf0XbSXLjeBhG+hvLIp9mqOVOnSAOOOBp3Xs6eQdu63FUyINFMykaw== X-Received: by 10.28.137.85 with SMTP id l82mr2224206wmd.109.1516719952812; Tue, 23 Jan 2018 07:05:52 -0800 (PST) Received: from schoudah-dev.vyatta.net ([137.221.143.78]) by smtp.gmail.com with ESMTPSA id a62sm7556228wmh.3.2018.01.23.07.05.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Jan 2018 07:05:52 -0800 (PST) From: Shweta Choudaha To: dev@dpdk.org Cc: Shweta Choudaha Date: Tue, 23 Jan 2018 15:05:32 +0000 Message-Id: <20180123150532.33912-2-shweta.choudaha@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180123150532.33912-1-shweta.choudaha@gmail.com> References: <1509978323-9879-1-git-send-email-shweta.choudaha@gmail.com> <20180123150532.33912-1-shweta.choudaha@gmail.com> Subject: [dpdk-dev] [PATCH v3 2/2] net/ixgbe : backplane port MDIO support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shweta Choudaha Initialize and implement MDIO read/write functions for backplane port (IXGBE_DEV_ID_X550EM_A_KR_L) to enable read/write registers via MDIO Signed-off-by: Shweta Choudaha Reviewed-by: Chas Williams Reviewed-by: Luca Boccassi --- drivers/net/ixgbe/base/ixgbe_x550.c | 54 ++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index f7401c060..885eaccfe 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -613,18 +613,62 @@ s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); } +/** + * ixgbe_read_phy_reg_x550em - Reads specified PHY register + * @hw: pointer to hardware structure + * @reg_addr: 32 bit address of PHY register to read + * @device_type: 5 bit device type + * @phy_data: Pointer to read data from PHY register + * + * Reads a value from a specified PHY register using the SWFW lock and PHY + * Token. The PHY Token is needed since the MDIO can be shared between MAC + * instances. + **/ STATIC s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 *phy_data) { - UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); - return IXGBE_NOT_IMPLEMENTED; + s32 status; + u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; + + DEBUGFUNC("ixgbe_read_phy_reg_x550em"); + + if (hw->mac.ops.acquire_swfw_sync(hw, mask)) + return IXGBE_ERR_SWFW_SYNC; + + status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); + + hw->mac.ops.release_swfw_sync(hw, mask); + + return status; } +/** + * ixgbe_write_phy_reg_x550em- Writes specified PHY register + * @hw: pointer to hardware structure + * @reg_addr: 32 bit PHY register to write + * @device_type: 5 bit device type + * @phy_data: Data to write to the PHY register + * + * Writes a value to specified PHY register using the SWFW lock and PHY Token. + * The PHY Token is needed since the MDIO can be shared between MAC instances. + **/ STATIC s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u16 phy_data) { - UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); - return IXGBE_NOT_IMPLEMENTED; + s32 status; + u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; + + DEBUGFUNC("ixgbe_write_phy_reg_x550em"); + + if (hw->mac.ops.acquire_swfw_sync(hw, mask) == IXGBE_SUCCESS) { + status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type, + phy_data); + hw->mac.ops.release_swfw_sync(hw, mask); + } else { + status = IXGBE_ERR_SWFW_SYNC; + } + + return status; } /** @@ -2423,6 +2467,8 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) phy->ops.write_reg = ixgbe_write_phy_reg_x550em; break; case ixgbe_phy_x550em_kr: + phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi_22; + phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi_22; phy->ops.setup_link = ixgbe_setup_kr_x550em; phy->ops.read_reg = ixgbe_read_phy_reg_x550em; phy->ops.write_reg = ixgbe_write_phy_reg_x550em;