From patchwork Thu Nov 23 17:37:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrien Mazarguil X-Patchwork-Id: 31607 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D2F042BF1; Thu, 23 Nov 2017 18:38:12 +0100 (CET) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by dpdk.org (Postfix) with ESMTP id 7963729D2 for ; Thu, 23 Nov 2017 18:38:10 +0100 (CET) Received: by mail-wm0-f67.google.com with SMTP id r68so18184359wmr.1 for ; Thu, 23 Nov 2017 09:38:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=+idziUpd2F8cOlDu6wGtbw764Woc1FqNuan0wbTxFYo=; b=COWE7PAS1cizFzxCWwpa3qKWt/jM8iRsgfNI9ZxK16TsOF2TpCip1+uCTii5n21I4D //QW5kbUh+QMtdOZX36BOa3KmpbtpUrXQwqHVo8x84fbunEh0fQn6NPO9gwLJAbw0LMy eb1UAmXcw5oyHKR1skSXRCWr+KmyiZMTtib2bvshxF/+InB/v8D+vVEZVLuvA9L/jkPd 6+HxTXxA3kjOEhQJT8DQq2CwHqoycWo9QBZnMpvFWah6RuFlB0XPPgOlV7EEQIyFFUxl FWrgI316QHcKbwUnQB0NjVIgaxF8xU1mDPPjwItQctzlZc3Vzxn+lq5XnOxqUu9jVSDM z2CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=+idziUpd2F8cOlDu6wGtbw764Woc1FqNuan0wbTxFYo=; b=aZFIfX//bYqTDmYcrr/Ri1RQC2oxzcwsphI+sxpwInVlwGBLY4vUk4FfoeXnHmGWo4 v0IYkeo9T388aTDT/W04cYyuUOjLNZ1utWqdSFVPFYWlVyFQ77LAIVBxu2u09y2kw0HM BRzlKjXF0i7FxGUpWAGZ8bKn31O+y2LIvqUlk0Ip2+lQtQfKLSKCo/9fHWwfi3/GfwiN Co+3rnqUI+h7sJ8W2uCcL9xGgherx2D8eHAYI0MiMFsCHFDn+iJgs8tF9V3Tcw0/ERiI iqXpBCF1SUKhtc6Zer7ZjUPWiLlbVOVl3aV7TgSyNaTnYg6sSjDyN48eMY9bo0t/SNMc QHsg== X-Gm-Message-State: AJaThX4hl4qwa4M5+PYtWFLv/iWZFhGAIblo+7vd4TugWsLh3cI8RNsz Ri/RxbOD8GQcYy+SzxQ6DasVDhxO X-Google-Smtp-Source: AGs4zMbK74IRrHL3JWTZ40YlGid4+QgQ6tsmWsMyG8MskSMpib78MrOD97Zjh3PWE3efrDu7lwILPA== X-Received: by 10.80.136.113 with SMTP id c46mr35258956edc.112.1511458690186; Thu, 23 Nov 2017 09:38:10 -0800 (PST) Received: from 6wind.com (host.78.145.23.62.rev.coltfrance.com. [62.23.145.78]) by smtp.gmail.com with ESMTPSA id u12sm14463327edk.45.2017.11.23.09.38.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Nov 2017 09:38:09 -0800 (PST) Date: Thu, 23 Nov 2017 18:37:58 +0100 From: Adrien Mazarguil To: Shahaf Shuler Cc: Ferruh Yigit , dev@dpdk.org, stable@dpdk.org, Neil Horman , Moti Haimovsky Message-ID: <20171123172640.28827-3-adrien.mazarguil@6wind.com> References: <1511272929-17955-1-git-send-email-adrien.mazarguil@6wind.com> <20171123172640.28827-1-adrien.mazarguil@6wind.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20171123172640.28827-1-adrien.mazarguil@6wind.com> X-Mailer: git-send-email 2.11.0 Subject: [dpdk-dev] [PATCH v2 2/5] net/mlx4: fix documentation in private structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" A couple of structure fields are not Doxygen-friendly. Fixes: 5db1d364086e ("net/mlx4: restore Tx checksum offloads") Cc: Moti Haimovsky Cc: stable@dpdk.org Signed-off-by: Adrien Mazarguil Acked-by: Neil Horman --- drivers/net/mlx4/mlx4.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx4/mlx4.h b/drivers/net/mlx4/mlx4.h index 3aeef87e9..77218580e 100644 --- a/drivers/net/mlx4/mlx4.h +++ b/drivers/net/mlx4/mlx4.h @@ -126,8 +126,8 @@ struct priv { uint32_t vf:1; /**< This is a VF device. */ uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */ uint32_t isolated:1; /**< Toggle isolated mode. */ - uint32_t hw_csum:1; /* Checksum offload is supported. */ - uint32_t hw_csum_l2tun:1; /* Checksum support for L2 tunnels. */ + uint32_t hw_csum:1; /**< Checksum offload is supported. */ + uint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */ struct rte_intr_handle intr_handle; /**< Port interrupt handle. */ struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */ LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */