From patchwork Fri Oct 13 00:02:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Monjalon X-Patchwork-Id: 30320 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 20AA81B5EA; Fri, 13 Oct 2017 02:03:01 +0200 (CEST) Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by dpdk.org (Postfix) with ESMTP id 50D521B3BA for ; Fri, 13 Oct 2017 02:02:57 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 0B01621969; Thu, 12 Oct 2017 20:02:57 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute1.internal (MEProxy); Thu, 12 Oct 2017 20:02:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= cc:date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc; s=mesmtp; bh=ztZQrH7SumqhCH iRuXPTGumJX8jBeRjurNgXuRw1H/w=; b=pKggRHjiJVhApZG9FlRQpPsV+mFUoG 3S8Uwqk5EngYdjK5idQi4BqEabiYwvjBL39HllXCmTxHTnL+B3onP9ORpwSS4fR8 FHayiuPsTcIX5OErcbPtj8hHUSgR7trOzoGYoLPVVRgB8/MF7iO1kp+wyks4mfLL 06Q7h9V9nosRo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=ztZQrH7SumqhCHiRuXPTGumJX8jBeRjurNgXuRw1H/w=; b=imGrl3AU w8zDPzIgIylKmKHf5Bf/yt6CdFhGWWaRZ8rZF+7554bwFU8iQVI+ryUbDKe/2+qP EhB3qQkD4qrUf2HbBfXUlzNCNuobro19+wyBYhxYaVYBwohvhiq9klPYLdtXgjpl io2lfebAXfD14l+keF/vC+rK5aj6DNrrvP3AYaK2CFcu+4eKlTxUUCrC/xXo09KT SLsaLb6qg8zs47eU03ncLyO8cQgxeQskK1IFwlygl+zUtBmYlovcoy7qpBwazvXt 5X4/R5UT+RNOoc+d0BJ154mNnUNKwQmtD5JZPty7XRMg3lDVjFZD0C04yJot4V7C 1AALPDZnECP2pg== X-ME-Sender: Received: from xps.monjalon.net (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 044AE24738; Thu, 12 Oct 2017 20:02:55 -0400 (EDT) From: Thomas Monjalon To: gowrishankar.m@linux.vnet.ibm.com, jerin.jacob@caviumnetworks.com, jianbo.liu@linaro.org, sergio.gonzalez.monroy@intel.com, bruce.richardson@intel.com Cc: dev@dpdk.org Date: Fri, 13 Oct 2017 02:02:47 +0200 Message-Id: <20171013000247.4158-5-thomas@monjalon.net> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171013000247.4158-1-thomas@monjalon.net> References: <20171013000247.4158-1-thomas@monjalon.net> Subject: [dpdk-dev] [PATCH 4/4] eal/x86: implement arch-specific TSC freq query X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sergio Gonzalez Monroy First, try to use CPUID Time Stamp Counter and Nominal Core Crystal Clock Information Leaf to determine the tsc hz on platforms that supports it (does not require privileged user). If the CPUID leaf is not available, then try to determine the tsc hz by reading the MSR 0xCE (requires privileged user). Default to the tsc hz estimation if both methods fail. Signed-off-by: Sergio Gonzalez Monroy Acked-by: Harry van Haaren Tested-by: Bruce Richardson --- lib/librte_eal/common/arch/x86/rte_cycles.c | 142 +++++++++++++++++++++++++++- 1 file changed, 141 insertions(+), 1 deletion(-) diff --git a/lib/librte_eal/common/arch/x86/rte_cycles.c b/lib/librte_eal/common/arch/x86/rte_cycles.c index 851fd0255..1049d6567 100644 --- a/lib/librte_eal/common/arch/x86/rte_cycles.c +++ b/lib/librte_eal/common/arch/x86/rte_cycles.c @@ -1,7 +1,147 @@ +/*- + * BSD LICENSE + * + * Copyright(c) 2017 Intel Corporation. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + #include "eal_private.h" +static unsigned int +rte_cpu_get_model(uint32_t fam_mod_step) +{ + uint32_t family, model, ext_model; + + family = (fam_mod_step >> 8) & 0xf; + model = (fam_mod_step >> 4) & 0xf; + + if (family == 6 || family == 15) { + ext_model = (fam_mod_step >> 16) & 0xf; + model += (ext_model << 4); + } + + return model; +} + +static int32_t +rdmsr(int msr, uint64_t *val) +{ +#ifdef RTE_EXEC_ENV_LINUXAPP + int fd; + int ret; + + fd = open("/dev/cpu/0/msr", O_RDONLY); + if (fd < 0) + return fd; + + ret = pread(fd, val, sizeof(uint64_t), msr); + + close(fd); + + return ret; +#else + return -1; +#endif +} + +static uint32_t +check_model_wsm_nhm(uint8_t model) +{ + switch (model) { + /* Westmere */ + case 0x25: + case 0x2C: + case 0x2F: + /* Nehalem */ + case 0x1E: + case 0x1F: + case 0x1A: + case 0x2E: + return 1; + } + + return 0; +} + +static uint32_t +check_model_gdm_dnv(uint8_t model) +{ + switch (model) { + /* Goldmont */ + case 0x5C: + /* Denverton */ + case 0x5F: + return 1; + } + + return 0; +} + uint64_t get_tsc_freq_arch(void) { - return 0; + uint64_t tsc_hz = 0; + uint32_t a, b, c, d, maxleaf; + uint8_t mult, model; + int32_t ret; + + /* + * Time Stamp Counter and Nominal Core Crystal Clock + * Information Leaf + */ + maxleaf = __get_cpuid_max(0, NULL); + + if (maxleaf >= 0x15) { + __cpuid(0x15, a, b, c, d); + + /* EBX : TSC/Crystal ratio, ECX : Crystal Hz */ + if (b && c) + return c * (b / a); + } + + __cpuid(0x1, a, b, c, d); + model = rte_cpu_get_model(a); + + if (check_model_wsm_nhm(model)) + mult = 133; + else if ((c & bit_AVX) || check_model_gdm_dnv(model)) + mult = 100; + else + return 0; + + ret = rdmsr(0xCE, &tsc_hz); + if (ret < 0) + return 0; + + return ((tsc_hz >> 8) & 0xff) * mult * 1E6; }