diff mbox series

[v5,15/22] net/ice: use mbuf descriptor accessors

Message ID 1708762927-14126-16-git-send-email-roretzla@linux.microsoft.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series stop using RTE_MARKER extensions |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tyler Retzlaff Feb. 24, 2024, 8:22 a.m. UTC 
  RTE_MARKER typedefs are a GCC extension unsupported by MSVC. Use
new rte_mbuf_rearm_data and rte_mbuf_rx_descriptor_fields1 accessors
that provide a compatible type pointer without using the marker fields.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
---
 drivers/net/ice/ice_rxtx_vec_avx2.c   | 16 ++++++++--------
 drivers/net/ice/ice_rxtx_vec_avx512.c | 16 ++++++++--------
 drivers/net/ice/ice_rxtx_vec_common.h |  4 +---
 drivers/net/ice/ice_rxtx_vec_sse.c    | 16 ++++++++--------
 4 files changed, 25 insertions(+), 27 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c b/drivers/net/ice/ice_rxtx_vec_avx2.c
index 6f6d790..fb3811a 100644
--- a/drivers/net/ice/ice_rxtx_vec_avx2.c
+++ b/drivers/net/ice/ice_rxtx_vec_avx2.c
@@ -596,13 +596,13 @@ 
 		rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 		rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 		/* write to mbuf */
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]),
 				    rearm6);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]),
 				    rearm4);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]),
 				    rearm2);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]),
 				    rearm0);
 
 		/* repeat for the odd mbufs */
@@ -625,13 +625,13 @@ 
 		rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 		rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 		/* again write to mbufs */
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]),
 				    rearm7);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]),
 				    rearm5);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]),
 				    rearm3);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]),
 				    rearm1);
 
 		/* extract and record EOP bit */
diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c b/drivers/net/ice/ice_rxtx_vec_avx512.c
index 04148e8..46d471f 100644
--- a/drivers/net/ice/ice_rxtx_vec_avx512.c
+++ b/drivers/net/ice/ice_rxtx_vec_avx512.c
@@ -597,13 +597,13 @@ 
 		rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 
 		/* write to mbuf */
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 6]),
 				    rearm6);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 4]),
 				    rearm4);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 2]),
 				    rearm2);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 0]),
 				    rearm0);
 
 		/* repeat for the odd mbufs */
@@ -627,13 +627,13 @@ 
 		rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 		rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 		/* again write to mbufs */
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 7]),
 				    rearm7);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 5]),
 				    rearm5);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 3]),
 				    rearm3);
-		_mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
+		_mm256_storeu_si256((__m256i *)rte_mbuf_rearm_data(rx_pkts[i + 1]),
 				    rearm1);
 
 		/* extract and record EOP bit */
diff --git a/drivers/net/ice/ice_rxtx_vec_common.h b/drivers/net/ice/ice_rxtx_vec_common.h
index 4b73465..c284d2d 100644
--- a/drivers/net/ice/ice_rxtx_vec_common.h
+++ b/drivers/net/ice/ice_rxtx_vec_common.h
@@ -232,7 +232,6 @@ 
 static inline int
 ice_rxq_vec_setup_default(struct ice_rx_queue *rxq)
 {
-	uintptr_t p;
 	struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
 
 	mb_def.nb_segs = 1;
@@ -242,8 +241,7 @@ 
 
 	/* prevent compiler reordering: rearm_data covers previous fields */
 	rte_compiler_barrier();
-	p = (uintptr_t)&mb_def.rearm_data;
-	rxq->mbuf_initializer = *(uint64_t *)p;
+	rxq->mbuf_initializer = *rte_mbuf_rearm_data(&mb_def);
 	return 0;
 }
 
diff --git a/drivers/net/ice/ice_rxtx_vec_sse.c b/drivers/net/ice/ice_rxtx_vec_sse.c
index 9a1b7e3..4a051b7 100644
--- a/drivers/net/ice/ice_rxtx_vec_sse.c
+++ b/drivers/net/ice/ice_rxtx_vec_sse.c
@@ -271,10 +271,10 @@ 
 			 offsetof(struct rte_mbuf, rearm_data) + 8);
 	RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 			 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
-	_mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
-	_mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
-	_mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
-	_mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
+	_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[0]), rearm0);
+	_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[1]), rearm1);
+	_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[2]), rearm2);
+	_mm_store_si128((__m128i *)rte_mbuf_rearm_data(rx_pkts[3]), rearm3);
 }
 
 static inline void
@@ -542,10 +542,10 @@ 
 
 		/* D.3 copy final 3,4 data to rx_pkts */
 		_mm_storeu_si128
-			((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
+			(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 3]),
 			 pkt_mb3);
 		_mm_storeu_si128
-			((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
+			(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 2]),
 			 pkt_mb2);
 
 		/* C* extract and record EOP bit */
@@ -569,9 +569,9 @@ 
 
 		/* D.3 copy final 1,2 data to rx_pkts */
 		_mm_storeu_si128
-			((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
+			(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos + 1]),
 			 pkt_mb1);
-		_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
+		_mm_storeu_si128(rte_mbuf_rx_descriptor_fields1(rx_pkts[pos]),
 				 pkt_mb0);
 		ice_rx_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
 		/* C.4 calc available number of desc */