diff mbox series

[v8,03/14] eal: use barrier intrinsics

Message ID	1682997341-2271-4-git-send-email-roretzla@linux.microsoft.com (mailing list archive)
State	Superseded, archived
Delegated to:	Thomas Monjalon
Headers	From: Tyler Retzlaff <roretzla@linux.microsoft.com> To: dev@dpdk.org Cc: bruce.richardson@intel.com, david.marchand@redhat.com, thomas@monjalon.net, mb@smartsharesystems.com, konstantin.ananyev@huawei.com, Tyler Retzlaff <roretzla@linux.microsoft.com> Subject: [PATCH v8 03/14] eal: use barrier intrinsics Date: Mon, 1 May 2023 20:15:30 -0700 Message-Id: <1682997341-2271-4-git-send-email-roretzla@linux.microsoft.com> In-Reply-To: <1682997341-2271-1-git-send-email-roretzla@linux.microsoft.com> References: <1680558751-17931-1-git-send-email-roretzla@linux.microsoft.com> <1682997341-2271-1-git-send-email-roretzla@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: dev-bounces@dpdk.org
Series	msvc integration changes \| [v8,00/14] msvc integration changes [v8,01/14] eal: use rdtsc intrinsic [v8,02/14] eal: use rtm and xtest intrinsics [v8,03/14] eal: use barrier intrinsics [v8,04/14] eal: use cpuid and cpuidex intrinsics [v8,05/14] eal: use umonitor umwait and tpause intrinsics [v8,06/14] eal: use prefetch intrinsics [v8,07/14] eal: use byte swap intrinsics [v8,08/14] eal: hide GCC extension based alignment markers [v8,09/14] eal: hide typedefs based on GCC vector extensions [v8,10/14] eal: expand most macros to empty when using MSVC [v8,11/14] eal: exclude exposure of rte atomic APIs for MSVC builds [v8,12/14] telemetry: avoid expanding versioned symbol macros on MSVC [v8,13/14] eal: always define MSVC as little endian [v8,14/14] eal: do not define typeof macro when building with MSVC

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Tyler Retzlaff May 2, 2023, 3:15 a.m. UTC

  Inline assembly is not supported for MSVC x64 instead expand
rte_compiler_barrier as _ReadWriteBarrier and for rte_smp_mb
_m_mfence intrinsics.

Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
---
 lib/eal/include/generic/rte_atomic.h | 4 ++++
 lib/eal/x86/include/rte_atomic.h     | 4 ++++
 2 files changed, 8 insertions(+)

diff mbox series

Patch

diff --git a/lib/eal/include/generic/rte_atomic.h b/lib/eal/include/generic/rte_atomic.h
index 234b268..e973184 100644
--- a/lib/eal/include/generic/rte_atomic.h
+++ b/lib/eal/include/generic/rte_atomic.h
@@ -116,9 +116,13 @@ 
  * Guarantees that operation reordering does not occur at compile time
  * for operations directly before and after the barrier.
  */
+#ifndef RTE_TOOLCHAIN_MSVC
 #define	rte_compiler_barrier() do {		\
 	asm volatile ("" : : : "memory");	\
 } while(0)
+#else
+#define rte_compiler_barrier() _ReadWriteBarrier()
+#endif
 
 /**
  * Synchronization fence between threads based on the specified memory order.
diff --git a/lib/eal/x86/include/rte_atomic.h b/lib/eal/x86/include/rte_atomic.h
index f2ee1a9..569d3ab 100644
--- a/lib/eal/x86/include/rte_atomic.h
+++ b/lib/eal/x86/include/rte_atomic.h
@@ -66,11 +66,15 @@ 
 static __rte_always_inline void
 rte_smp_mb(void)
 {
+#ifndef RTE_TOOLCHAIN_MSVC
 #ifdef RTE_ARCH_I686
 	asm volatile("lock addl $0, -128(%%esp); " ::: "memory");
 #else
 	asm volatile("lock addl $0, -128(%%rsp); " ::: "memory");
 #endif
+#else
+	_mm_mfence();
+#endif
 }
 
 #define rte_io_mb() rte_mb()