From patchwork Fri Jun 25 05:36:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 94821 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53595A0C40; Fri, 25 Jun 2021 07:38:55 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5F6F941102; Fri, 25 Jun 2021 07:38:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 795D9410EA for ; Fri, 25 Jun 2021 07:38:28 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15P5Ze0a015880; Thu, 24 Jun 2021 22:38:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=VF9UWo6C3GVBfNdBVZ1sbxf/X+IKHyj6MMG0bRMl1qA=; b=UYE1+o1M98EdYauaCYTVgMjRpUmbtnsekPFBsqZGI6uPMYrm9YVlO3Xwur9T+TlO6gzp 9Ge3uzmMa8Ixp6mK5bpl0Cjf0HGSuhIBqjvQB9hT7bf1IP8BYJZR7/ttMxkW4pPNkhJ3 bKtspg/rkXMWfu3HDDToISP9NmWnMYD+eiwtfrMEDGqtdLV44g3iIlHdzGr1qrD1orBF snQC9Ei3DREOW2m8H0Y28p8rVwi7uRF5kIUmJF3Vl+UgNGsDU/eNXSGy3ZC3/P+KHRkx /7EBdVj5uqZibuL+iVZ55bJQ+nS35fJ3LYm3ZmGa/hCQpVlN2VGlXkQkDcnkUYP/jvks DQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39d241sg7u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Jun 2021 22:38:27 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Jun 2021 22:38:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 24 Jun 2021 22:38:25 -0700 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 4354E3F7041; Thu, 24 Jun 2021 22:38:21 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Kiran Kumar Kokkilagadda , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Fri, 25 Jun 2021 11:06:47 +0530 Message-ID: <1624599410-29689-16-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624599410-29689-1-git-send-email-anoobj@marvell.com> References: <1624599410-29689-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: BWa8z9UjUCiV5F4pZf7ASeUvojznJD9f X-Proofpoint-ORIG-GUID: BWa8z9UjUCiV5F4pZf7ASeUvojznJD9f X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 Subject: [dpdk-dev] [PATCH v2 15/17] common/cnxk: add EC grp static vectors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar Kokkilagadda EC group static vectors are required for CPT asymmetric operations. Signed-off-by: Anoob Joseph Signed-off-by: Kiran Kumar Kokkilagadda --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_ae.c | 142 ++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_ae.h | 7 ++ drivers/common/cnxk/version.map | 2 + 4 files changed, 152 insertions(+) create mode 100644 drivers/common/cnxk/roc_ae.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 181b58e..4c5d318 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -11,6 +11,7 @@ endif config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( + 'roc_ae.c', 'roc_ae_fpm_tables.c', 'roc_cpt.c', 'roc_cpt_debug.c', diff --git a/drivers/common/cnxk/roc_ae.c b/drivers/common/cnxk/roc_ae.c new file mode 100644 index 0000000..cf3f7fc --- /dev/null +++ b/drivers/common/cnxk/roc_ae.c @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" + +#define AE_EC_GRP_TBL_NAME "ae_ec_grp_tbl" + +struct ae_ec_grp_tbl { + uint64_t refcount; + uint8_t ec_grp_tbl[]; +}; + +const struct roc_ae_ec_group ae_ec_grp[ROC_AE_EC_ID_PMAX] = { + { + .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, + .length = 24}, + .order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x99, 0xDE, 0xF8, 0x36, 0x14, 0x6B, + 0xC9, 0xB1, 0xB4, 0xD2, 0x28, 0x31}, + .length = 24}, + }, + { + .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, + .length = 28}, + .order = {.data = {0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, + 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF, + 0X16, 0XA2, 0XE0, 0XB8, 0XF0, 0X3E, 0X13, + 0XDD, 0X29, 0X45, 0X5C, 0X5C, 0X2A, 0X3D}, + .length = 28}, + }, + { + .prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF}, + .length = 32}, + .order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xBC, 0xE6, 0xFA, 0xAD, 0xA7, + 0x17, 0x9E, 0x84, 0xF3, 0xB9, 0xCA, 0xC2, + 0xFC, 0x63, 0x25, 0x51}, + .length = 32}, + }, + {.prime = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF}, + .length = 48}, + .order = {.data = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xC7, 0x63, 0x4D, 0x81, 0xF4, 0x37, 0x2D, 0xDF, + 0x58, 0x1A, 0x0D, 0xB2, 0x48, 0xB0, 0xA7, 0x7A, + 0xEC, 0xEC, 0x19, 0x6A, 0xCC, 0xC5, 0x29, 0x73}, + .length = 48}}, + {.prime = {.data = {0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF}, + .length = 66}, + .order = {.data = {0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFA, 0x51, 0x86, 0x87, 0x83, 0xBF, 0x2F, + 0x96, 0x6B, 0x7F, 0xCC, 0x01, 0x48, 0xF7, 0x09, + 0xA5, 0xD0, 0x3B, 0xB5, 0xC9, 0xB8, 0x89, 0x9C, + 0x47, 0xAE, 0xBB, 0x6F, 0xB7, 0x1E, 0x91, 0x38, + 0x64, 0x09}, + .length = 66}}}; + +int +roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl) +{ + const char name[] = AE_EC_GRP_TBL_NAME; + struct ae_ec_grp_tbl *ec_grp; + const struct plt_memzone *mz; + int i, len = 0; + uint8_t *data; + + if (tbl == NULL) + return -EINVAL; + + len = sizeof(ae_ec_grp); + + mz = plt_memzone_lookup(name); + if (mz == NULL) { + /* Create memzone first time */ + mz = plt_memzone_reserve_cache_align( + name, len + sizeof(struct ae_ec_grp_tbl)); + if (mz == NULL) + return -ENOMEM; + } + + ec_grp = mz->addr; + + if (__atomic_fetch_add(&ec_grp->refcount, 1, __ATOMIC_SEQ_CST) != 0) + return 0; + + data = PLT_PTR_ADD(mz->addr, sizeof(uint64_t)); + + for (i = 0; i < ROC_AE_EC_ID_PMAX; i++) { + memcpy(data, &ae_ec_grp[i], sizeof(struct roc_ae_ec_group)); + tbl[i] = (struct roc_ae_ec_group *)data; + data += sizeof(struct roc_ae_ec_group); + } + + return 0; +} + +void +roc_ae_ec_grp_put(void) +{ + const char name[] = AE_EC_GRP_TBL_NAME; + const struct plt_memzone *mz; + struct ae_ec_grp_tbl *ec_grp; + + mz = plt_memzone_lookup(name); + if (mz == NULL) + return; + + ec_grp = mz->addr; + /* Decrement number of devices using EC grp table */ + if (__atomic_sub_fetch(&ec_grp->refcount, 1, __ATOMIC_SEQ_CST) == 0) + plt_memzone_free(mz); +} diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h index c549e18..5072cc5 100644 --- a/drivers/common/cnxk/roc_ae.h +++ b/drivers/common/cnxk/roc_ae.h @@ -53,4 +53,11 @@ struct roc_ae_ec_ctx { uint8_t curveid; }; +/* Buffer pointer */ +struct roc_ae_buf_ptr { + void *vaddr; +}; + +int __roc_api roc_ae_ec_grp_get(struct roc_ae_ec_group **tbl); +void __roc_api roc_ae_ec_grp_put(void); #endif /* __ROC_AE_H__ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 7a3b4a6..9611217 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -10,6 +10,8 @@ INTERNAL { cnxk_logtype_sso; cnxk_logtype_tim; cnxk_logtype_tm; + roc_ae_ec_grp_get; + roc_ae_ec_grp_put; roc_ae_fpm_get; roc_ae_fpm_put; roc_clk_freq_get;