From patchwork Fri Jun 25 05:36:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anoob Joseph X-Patchwork-Id: 94818 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 78260A0C40; Fri, 25 Jun 2021 07:38:33 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 95CED40E25; Fri, 25 Jun 2021 07:38:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A0BCD40698 for ; Fri, 25 Jun 2021 07:38:12 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15P5ab9f018611; Thu, 24 Jun 2021 22:38:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=R6wgRFBMVl3nV9xn/KhpRg7CsbfNsOu8ryQI5lsaEhA=; b=c0rU2ZTjZ4/vYkCX60qHfpgChmA/Yf/knVMZUBaawrdDFDi1j9gBAfjg4ywda3SkJ9ip 0aXvCk4x70C9TZOtp3hdkAMYveDTlBPw3/JIBHVae0fZXeKzmiF+e6F5/aPGDyvS/ybZ KM49c6FaHoKGeTqXq1vD3D10HAb4+VQDcyMtOYArz38SCm9qQqBCp1fWESNmw1jzkdgN 7JMpU8qaH/jym92zre13OY2O+Qt9eKkHJhEEoTdwTDrm3HW9k9v5gxzU3W4/nQ85ldqB TrYMnvs3n3lzmD2ICGlMaX5xoGYavRy1tZMbk41MFmYko/kjcXj1x1gEZtuB+o2A62x0 Eg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 39d24dhh60-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Jun 2021 22:38:11 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Jun 2021 22:38:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 24 Jun 2021 22:38:10 -0700 Received: from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218]) by maili.marvell.com (Postfix) with ESMTP id 077C73F706F; Thu, 24 Jun 2021 22:38:06 -0700 (PDT) From: Anoob Joseph To: Akhil Goyal , Thomas Monjalon CC: Kiran Kumar Kokkilagadda , Jerin Jacob , Ankur Dwivedi , Tejasree Kondoj , , Anoob Joseph Date: Fri, 25 Jun 2021 11:06:44 +0530 Message-ID: <1624599410-29689-13-git-send-email-anoobj@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624599410-29689-1-git-send-email-anoobj@marvell.com> References: <1624599410-29689-1-git-send-email-anoobj@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: OAOS0skSDAoSj02MhJFW9gxI473vmmw9 X-Proofpoint-ORIG-GUID: OAOS0skSDAoSj02MhJFW9gxI473vmmw9 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-25_01:2021-06-24, 2021-06-25 signatures=0 Subject: [dpdk-dev] [PATCH v2 12/17] common/cnxk: add AE microcode defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar Kokkilagadda Microcode AE opcodes support asymmetric operations. Add defines and structs defined by microcode. Signed-off-by: Anoob Joseph Signed-off-by: Kiran Kumar Kokkilagadda --- drivers/common/cnxk/roc_ae.h | 56 +++++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_api.h | 1 + drivers/common/cnxk/roc_cpt.h | 3 +++ 3 files changed, 60 insertions(+) create mode 100644 drivers/common/cnxk/roc_ae.h diff --git a/drivers/common/cnxk/roc_ae.h b/drivers/common/cnxk/roc_ae.h new file mode 100644 index 0000000..c549e18 --- /dev/null +++ b/drivers/common/cnxk/roc_ae.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef __ROC_AE_H__ +#define __ROC_AE_H__ + +/* AE opcodes */ +#define ROC_AE_MAJOR_OP_MODEX 0x03 +#define ROC_AE_MAJOR_OP_ECDSA 0x04 +#define ROC_AE_MAJOR_OP_ECC 0x05 +#define ROC_AE_MINOR_OP_MODEX 0x01 +#define ROC_AE_MINOR_OP_PKCS_ENC 0x02 +#define ROC_AE_MINOR_OP_PKCS_ENC_CRT 0x03 +#define ROC_AE_MINOR_OP_PKCS_DEC 0x04 +#define ROC_AE_MINOR_OP_PKCS_DEC_CRT 0x05 +#define ROC_AE_MINOR_OP_MODEX_CRT 0x06 +#define ROC_AE_MINOR_OP_ECDSA_SIGN 0x01 +#define ROC_AE_MINOR_OP_ECDSA_VERIFY 0x02 +#define ROC_AE_MINOR_OP_ECC_UMP 0x03 + +/** + * Enumeration roc_ae_ec_id + * + * Enumerates supported elliptic curves + */ +typedef enum { + ROC_AE_EC_ID_P192 = 0, + ROC_AE_EC_ID_P224 = 1, + ROC_AE_EC_ID_P256 = 2, + ROC_AE_EC_ID_P384 = 3, + ROC_AE_EC_ID_P521 = 4, + ROC_AE_EC_ID_PMAX = 5 +} roc_ae_ec_id; + +/* Prime and order fields of built-in elliptic curves */ +struct roc_ae_ec_group { + struct { + /* P521 maximum length */ + uint8_t data[66]; + unsigned int length; + } prime; + + struct { + /* P521 maximum length */ + uint8_t data[66]; + unsigned int length; + } order; +}; + +struct roc_ae_ec_ctx { + /* Prime length defined by microcode for EC operations */ + uint8_t curveid; +}; + +#endif /* __ROC_AE_H__ */ diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index d545bb9..546818d 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -110,6 +110,7 @@ #include "roc_cpt.h" /* CPT microcode */ +#include "roc_ae.h" #include "roc_ie_on.h" #include "roc_ie_ot.h" #include "roc_se.h" diff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h index cb2838e..5577fea 100644 --- a/drivers/common/cnxk/roc_cpt.h +++ b/drivers/common/cnxk/roc_cpt.h @@ -7,6 +7,9 @@ #include "roc_api.h" +#define ROC_AE_CPT_BLOCK_TYPE1 0 +#define ROC_AE_CPT_BLOCK_TYPE2 1 + /* Default engine groups */ #define ROC_CPT_DFLT_ENG_GRP_SE 0UL #define ROC_CPT_DFLT_ENG_GRP_SE_IE 1UL