diff mbox series

[v16,4/8] eal/arm: update CPU flags

Message ID	1618995020-4775-5-git-send-email-juraj.linkes@pantheon.tech (mailing list archive)
State	Superseded, archived
Delegated to:	Thomas Monjalon
Headers	From: =?utf-8?q?Juraj_Linke=C5=A1?= <juraj.linkes@pantheon.tech> To: thomas@monjalon.net, david.marchand@redhat.com, bruce.richardson@intel.com, aconole@redhat.com, maicolgabriel@hotmail.com Cc: juraj.linkes@pantheon.tech, dev@dpdk.org Date: Wed, 21 Apr 2021 10:50:16 +0200 Message-Id: <1618995020-4775-5-git-send-email-juraj.linkes@pantheon.tech> In-Reply-To: <1618995020-4775-1-git-send-email-juraj.linkes@pantheon.tech> References: <1615988163-17371-1-git-send-email-juraj.linkes@pantheon.tech> <1618995020-4775-1-git-send-email-juraj.linkes@pantheon.tech> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v16 4/8] eal/arm: update CPU flags Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	aarch64 -> aarch32 cross compilation support \| [v16,0/8] aarch64 -> aarch32 cross compilation support [v16,1/8] net/sfc: fix aarch32 build [v16,2/8] net/bnxt: fix aarch32 build [v16,3/8] net/virtio: fix aarch32 build [v16,4/8] eal/arm: update CPU flags [v16,5/8] build: add aarch32 meson build flags [v16,6/8] build: add aarch32 to meson cross-compilation [v16,7/8] ci: add aarch64 -> aarch32 cross compiling jobs [v16,8/8] doc: add aarch32 build guidance

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Juraj Linkeš April 21, 2021, 8:50 a.m. UTC

  There are two execution states on armv8 architecture, aarch64 and
aarch32. Add PLATFORM_STR for the latter and update RTE_ARCH_* flags
according to e9b97392640.

Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
---
 lib/librte_eal/arm/include/rte_cpuflags_32.h | 1 +
 lib/librte_eal/arm/rte_cpuflags.c            | 9 +++++++--
 2 files changed, 8 insertions(+), 2 deletions(-)

Comments

Juraj Linkeš April 21, 2021, 2:28 p.m. UTC | #1

Addining Jerin, Jan and Ruifeng

> -----Original Message-----
> From: Juraj Linkeš <juraj.linkes@pantheon.tech>
> Sent: Wednesday, April 21, 2021 10:50 AM
> To: thomas@monjalon.net; david.marchand@redhat.com;
> bruce.richardson@intel.com; aconole@redhat.com;
> maicolgabriel@hotmail.com
> Cc: Juraj Linkeš <juraj.linkes@pantheon.tech>; dev@dpdk.org
> Subject: [PATCH v16 4/8] eal/arm: update CPU flags
> 
> There are two execution states on armv8 architecture, aarch64 and aarch32.
> Add PLATFORM_STR for the latter and update RTE_ARCH_* flags according to
> e9b97392640.
> 
> Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
> ---
>  lib/librte_eal/arm/include/rte_cpuflags_32.h | 1 +
>  lib/librte_eal/arm/rte_cpuflags.c            | 9 +++++++--
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/librte_eal/arm/include/rte_cpuflags_32.h
> b/lib/librte_eal/arm/include/rte_cpuflags_32.h
> index b5347be1ec..4e254428a2 100644
> --- a/lib/librte_eal/arm/include/rte_cpuflags_32.h
> +++ b/lib/librte_eal/arm/include/rte_cpuflags_32.h
> @@ -41,6 +41,7 @@ enum rte_cpu_flag_t {
>  	RTE_CPUFLAG_SHA2,
>  	RTE_CPUFLAG_CRC32,
>  	RTE_CPUFLAG_V7L,
> +	RTE_CPUFLAG_V8L,
>  	/* The last item */
>  	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */  };
> diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c
> index e3a53bcece..4167a1a302 100644
> --- a/lib/librte_eal/arm/rte_cpuflags.c
> +++ b/lib/librte_eal/arm/rte_cpuflags.c
> @@ -46,8 +46,12 @@ struct feature_entry {  #define FEAT_DEF(name, reg, bit) \
>  	[RTE_CPUFLAG_##name] = {reg, bit, #name},
> 
> +#ifdef RTE_ARCH_32
>  #ifdef RTE_ARCH_ARMv7
>  #define PLATFORM_STR "v7l"
> +#elif defined RTE_ARCH_ARMv8_AARCH32
> +#define PLATFORM_STR "v8l"
> +#endif
>  typedef Elf32_auxv_t _Elfx_auxv_t;
> 
>  const struct feature_entry rte_cpu_feature_table[] = { @@ -79,9 +83,10 @@
> const struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(SHA2,      REG_HWCAP2,   3)
>  	FEAT_DEF(CRC32,     REG_HWCAP2,   4)
>  	FEAT_DEF(V7L,       REG_PLATFORM, 0)
> +	FEAT_DEF(V8L,       REG_PLATFORM, 0)
>  };
> 
> -#elif defined RTE_ARCH_ARM64
> +#elif defined RTE_ARCH_64
>  #define PLATFORM_STR "aarch64"
>  typedef Elf64_auxv_t _Elfx_auxv_t;
> 
> @@ -108,7 +113,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(SVEF32MM,	REG_HWCAP2,   10)
>  	FEAT_DEF(SVEF64MM,	REG_HWCAP2,   11)
>  	FEAT_DEF(SVEBF16,	REG_HWCAP2,   12)
> -	FEAT_DEF(AARCH64,	REG_PLATFORM, 1)
> +	FEAT_DEF(AARCH64,	REG_PLATFORM, 0)
>  };
>  #endif /* RTE_ARCH */
> 
> --
> 2.20.1

Ruifeng Wang April 22, 2021, 5:32 a.m. UTC | #2

> -----Original Message-----
> From: Juraj Linkeš <juraj.linkes@pantheon.tech>
> Sent: Wednesday, April 21, 2021 10:28 PM
> To: Juraj Linkeš <juraj.linkes@pantheon.tech>; thomas@monjalon.net;
> david.marchand@redhat.com; bruce.richardson@intel.com;
> aconole@redhat.com; maicolgabriel@hotmail.com; Ruifeng Wang
> <Ruifeng.Wang@arm.com>; jerinj@marvell.com; viktorin@rehivetech.com
> Cc: dev@dpdk.org
> Subject: RE: [PATCH v16 4/8] eal/arm: update CPU flags
> 
> Addining Jerin, Jan and Ruifeng
> 
> > -----Original Message-----
> > From: Juraj Linkeš <juraj.linkes@pantheon.tech>
> > Sent: Wednesday, April 21, 2021 10:50 AM
> > To: thomas@monjalon.net; david.marchand@redhat.com;
> > bruce.richardson@intel.com; aconole@redhat.com;
> > maicolgabriel@hotmail.com
> > Cc: Juraj Linkeš <juraj.linkes@pantheon.tech>; dev@dpdk.org
> > Subject: [PATCH v16 4/8] eal/arm: update CPU flags
> >
> > There are two execution states on armv8 architecture, aarch64 and aarch32.
> > Add PLATFORM_STR for the latter and update RTE_ARCH_* flags according
> > to e9b97392640.
> >
> > Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
> > ---
> >  lib/librte_eal/arm/include/rte_cpuflags_32.h | 1 +
> >  lib/librte_eal/arm/rte_cpuflags.c            | 9 +++++++--
> >  2 files changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/lib/librte_eal/arm/include/rte_cpuflags_32.h
> > b/lib/librte_eal/arm/include/rte_cpuflags_32.h
> > index b5347be1ec..4e254428a2 100644
> > --- a/lib/librte_eal/arm/include/rte_cpuflags_32.h
> > +++ b/lib/librte_eal/arm/include/rte_cpuflags_32.h
> > @@ -41,6 +41,7 @@ enum rte_cpu_flag_t {
> >  	RTE_CPUFLAG_SHA2,
> >  	RTE_CPUFLAG_CRC32,
> >  	RTE_CPUFLAG_V7L,
> > +	RTE_CPUFLAG_V8L,
> >  	/* The last item */
> >  	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */  };
> > diff --git a/lib/librte_eal/arm/rte_cpuflags.c
> > b/lib/librte_eal/arm/rte_cpuflags.c
> > index e3a53bcece..4167a1a302 100644
> > --- a/lib/librte_eal/arm/rte_cpuflags.c
> > +++ b/lib/librte_eal/arm/rte_cpuflags.c
> > @@ -46,8 +46,12 @@ struct feature_entry {  #define FEAT_DEF(name, reg,
> bit) \
> >  	[RTE_CPUFLAG_##name] = {reg, bit, #name},
> >
> > +#ifdef RTE_ARCH_32
> >  #ifdef RTE_ARCH_ARMv7
> >  #define PLATFORM_STR "v7l"
> > +#elif defined RTE_ARCH_ARMv8_AARCH32
> > +#define PLATFORM_STR "v8l"
> > +#endif
> >  typedef Elf32_auxv_t _Elfx_auxv_t;
> >
> >  const struct feature_entry rte_cpu_feature_table[] = { @@ -79,9
> > +83,10 @@ const struct feature_entry rte_cpu_feature_table[] = {
> >  	FEAT_DEF(SHA2,      REG_HWCAP2,   3)
> >  	FEAT_DEF(CRC32,     REG_HWCAP2,   4)
> >  	FEAT_DEF(V7L,       REG_PLATFORM, 0)
> > +	FEAT_DEF(V8L,       REG_PLATFORM, 0)

#ifdef are needed for ARMv7 and AARCH32 to define platform flags respectively. 

> >  };
> >
> > -#elif defined RTE_ARCH_ARM64
> > +#elif defined RTE_ARCH_64
> >  #define PLATFORM_STR "aarch64"
> >  typedef Elf64_auxv_t _Elfx_auxv_t;
> >
> > @@ -108,7 +113,7 @@ const struct feature_entry rte_cpu_feature_table[]
> = {
> >  	FEAT_DEF(SVEF32MM,	REG_HWCAP2,   10)
> >  	FEAT_DEF(SVEF64MM,	REG_HWCAP2,   11)
> >  	FEAT_DEF(SVEBF16,	REG_HWCAP2,   12)
> > -	FEAT_DEF(AARCH64,	REG_PLATFORM, 1)
> > +	FEAT_DEF(AARCH64,	REG_PLATFORM, 0)

This is a bug fix. Should be in a separate patch?

> >  };
> >  #endif /* RTE_ARCH */
> >
> > --
> > 2.20.1

diff mbox series

Patch

diff --git a/lib/librte_eal/arm/include/rte_cpuflags_32.h b/lib/librte_eal/arm/include/rte_cpuflags_32.h
index b5347be1ec..4e254428a2 100644
--- a/lib/librte_eal/arm/include/rte_cpuflags_32.h
+++ b/lib/librte_eal/arm/include/rte_cpuflags_32.h
@@ -41,6 +41,7 @@  enum rte_cpu_flag_t {
 	RTE_CPUFLAG_SHA2,
 	RTE_CPUFLAG_CRC32,
 	RTE_CPUFLAG_V7L,
+	RTE_CPUFLAG_V8L,
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
 };
diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c
index e3a53bcece..4167a1a302 100644
--- a/lib/librte_eal/arm/rte_cpuflags.c
+++ b/lib/librte_eal/arm/rte_cpuflags.c
@@ -46,8 +46,12 @@  struct feature_entry {
 #define FEAT_DEF(name, reg, bit) \
 	[RTE_CPUFLAG_##name] = {reg, bit, #name},
 
+#ifdef RTE_ARCH_32
 #ifdef RTE_ARCH_ARMv7
 #define PLATFORM_STR "v7l"
+#elif defined RTE_ARCH_ARMv8_AARCH32
+#define PLATFORM_STR "v8l"
+#endif
 typedef Elf32_auxv_t _Elfx_auxv_t;
 
 const struct feature_entry rte_cpu_feature_table[] = {
@@ -79,9 +83,10 @@  const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(SHA2,      REG_HWCAP2,   3)
 	FEAT_DEF(CRC32,     REG_HWCAP2,   4)
 	FEAT_DEF(V7L,       REG_PLATFORM, 0)
+	FEAT_DEF(V8L,       REG_PLATFORM, 0)
 };
 
-#elif defined RTE_ARCH_ARM64
+#elif defined RTE_ARCH_64
 #define PLATFORM_STR "aarch64"
 typedef Elf64_auxv_t _Elfx_auxv_t;
 
@@ -108,7 +113,7 @@  const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(SVEF32MM,	REG_HWCAP2,   10)
 	FEAT_DEF(SVEF64MM,	REG_HWCAP2,   11)
 	FEAT_DEF(SVEBF16,	REG_HWCAP2,   12)
-	FEAT_DEF(AARCH64,	REG_PLATFORM, 1)
+	FEAT_DEF(AARCH64,	REG_PLATFORM, 0)
 };
 #endif /* RTE_ARCH */