From patchwork Fri Oct 2 14:11:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Ma" X-Patchwork-Id: 79539 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 27E31A04B5; Fri, 2 Oct 2020 16:12:43 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 97A8E1D673; Fri, 2 Oct 2020 16:12:23 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id CEE031D16E for ; Fri, 2 Oct 2020 16:12:19 +0200 (CEST) IronPort-SDR: 2+ZLe1L99E1kIy6qvbrxAsKoAolEF16yfTN5dJmqqbg1HqZKdvV0+wW2Q7KzLKqcMPdjm0nxFb Z/Ru/YmpHdKA== X-IronPort-AV: E=McAfee;i="6000,8403,9761"; a="160324307" X-IronPort-AV: E=Sophos;i="5.77,327,1596524400"; d="scan'208";a="160324307" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Oct 2020 07:12:09 -0700 IronPort-SDR: S2DR2un0vnv8jFzOnkV6GJWpcZ3NFEwkVX5rVSDKRQazsblk03+G5iH8BcOKyucDq7KuzHwqlU MomCFYLoBDPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,327,1596524400"; d="scan'208";a="294853278" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga007.fm.intel.com with ESMTP; 02 Oct 2020 07:12:07 -0700 Received: from sivswdev09.ir.intel.com (sivswdev09.ir.intel.com [10.237.217.48]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 092EC7ld003634; Fri, 2 Oct 2020 15:12:07 +0100 Received: from sivswdev09.ir.intel.com (localhost [127.0.0.1]) by sivswdev09.ir.intel.com with ESMTP id 092EC7H4025390; Fri, 2 Oct 2020 15:12:07 +0100 Received: (from lma25@localhost) by sivswdev09.ir.intel.com with LOCAL id 092EC7CR025386; Fri, 2 Oct 2020 15:12:07 +0100 From: Liang Ma To: dev@dpdk.org Cc: david.hunt@intel.com, stephen@networkplumber.org, konstantin.ananyev@intel.com, Liang Ma , Anatoly Burakov Date: Fri, 2 Oct 2020 15:11:50 +0100 Message-Id: <1601647919-25312-1-git-send-email-liang.j.ma@intel.com> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1599214740-3927-1-git-send-email-liang.j.ma@intel.com> References: <1599214740-3927-1-git-send-email-liang.j.ma@intel.com> Subject: [dpdk-dev] [PATCH v4 01/10] eal: add new x86 cpuid support for WAITPKG X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add new x86 cpuid support for WAITPKG. This flag indicate processor support umwait/umonitor/tpause instruction. Signed-off-by: Liang Ma Signed-off-by: Anatoly Burakov Acked-by: Konstantin Ananyev --- lib/librte_eal/x86/include/rte_cpuflags.h | 2 ++ lib/librte_eal/x86/rte_cpuflags.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/lib/librte_eal/x86/include/rte_cpuflags.h b/lib/librte_eal/x86/include/rte_cpuflags.h index c1d20364d1..5041a830a7 100644 --- a/lib/librte_eal/x86/include/rte_cpuflags.h +++ b/lib/librte_eal/x86/include/rte_cpuflags.h @@ -132,6 +132,8 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_MOVDIR64B, /**< Direct Store Instructions 64B */ RTE_CPUFLAG_AVX512VP2INTERSECT, /**< AVX512 Two Register Intersection */ + /**< UMWAIT/TPAUSE Instructions */ + RTE_CPUFLAG_WAITPKG, /**< UMINITOR/UMWAIT/TPAUSE */ /* The last item */ RTE_CPUFLAG_NUMFLAGS, /**< This should always be the last! */ }; diff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c index 30439e7951..0325c4b93b 100644 --- a/lib/librte_eal/x86/rte_cpuflags.c +++ b/lib/librte_eal/x86/rte_cpuflags.c @@ -110,6 +110,8 @@ const struct feature_entry rte_cpu_feature_table[] = { FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16) FEAT_DEF(RDSEED, 0x00000007, 0, RTE_REG_EBX, 18) + FEAT_DEF(WAITPKG, 0x00000007, 0, RTE_REG_ECX, 5) + FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX, 0) FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX, 4)