@@ -1720,3 +1720,81 @@ struct mlx5_devx_obj *
return 0;
}
+/**
+ * Write to RXP registers.
+ *
+ * @param ctx
+ * ibv device handle
+ * @param engine_id
+ * Chooses on which engine the register will be written..
+ * @param addr
+ * Register address.
+ * @param data
+ * Data to be written to the register.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t data)
+{
+ uint32_t out[MLX5_ST_SZ_DW(set_regexp_register_out)] = {0};
+ uint32_t in[MLX5_ST_SZ_DW(set_regexp_register_in)] = {0};
+ int ret;
+
+ MLX5_SET(set_regexp_register_in, in, opcode,
+ MLX5_CMD_SET_REGEX_REGISTERS);
+ MLX5_SET(set_regexp_register_in, in, engine_id, engine_id);
+ MLX5_SET(set_regexp_register_in, in, register_address, addr);
+ MLX5_SET(set_regexp_register_in, in, register_data, data);
+
+ ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
+ sizeof(out));
+ if (ret) {
+ DRV_LOG(ERR, "Set regexp register failed %d", ret);
+ rte_errno = errno;
+ return -errno;
+ }
+ return 0;
+}
+
+
+/**
+ * Read from RXP registers
+ *
+ * @param ctx
+ * ibv device handle
+ * @param engine_id
+ * Chooses from which engine to read.
+ * @param addr
+ * Register address.
+ * @param data
+ * Output containing the pointer to the data..
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t *data)
+{
+ uint32_t out[MLX5_ST_SZ_DW(query_regexp_register_out)] = {0};
+ uint32_t in[MLX5_ST_SZ_DW(query_regexp_register_in)] = {0};
+ int ret;
+
+ MLX5_SET(query_regexp_register_in, in, opcode,
+ MLX5_CMD_QUERY_REGEX_REGISTERS);
+ MLX5_SET(query_regexp_register_in, in, engine_id, engine_id);
+ MLX5_SET(query_regexp_register_in, in, register_address, addr);
+
+ ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
+ sizeof(out));
+ if (ret) {
+ DRV_LOG(ERR, "Query regexp register failed %d", ret);
+ rte_errno = errno;
+ return -errno;
+ }
+ *data = MLX5_GET(query_regexp_register_out, out, register_data);
+ return 0;
+}
@@ -374,6 +374,10 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
__rte_internal
int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
struct mlx5_devx_rqt_attr *rqt_attr);
+int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t data);
+int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t *data);
/**
* Create virtio queue counters object DevX API.
@@ -408,4 +412,10 @@ int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
__rte_internal
int mlx5_devx_regex_database_program(void *ctx, uint8_t engine,
uint32_t umem_id, uint64_t umem_offset);
+__rte_internal
+int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t *data);
+__rte_internal
+int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t data);
#endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */
@@ -38,6 +38,8 @@ INTERNAL {
mlx5_devx_regex_database_program;
mlx5_devx_regex_database_resume;
mlx5_devx_regex_database_stop;
+ mlx5_devx_regex_register_read;
+ mlx5_devx_regex_register_write;
mlx5_get_ifname_sysfs;
mlx5_get_dbr;