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Wed, 11 Dec 2019 09:52:04 +0000 Received: from DB7PR04MB5196.eurprd04.prod.outlook.com ([fe80::cdaa:fcae:322b:59ed]) by DB7PR04MB5196.eurprd04.prod.outlook.com ([fe80::cdaa:fcae:322b:59ed%7]) with mapi id 15.20.2516.018; Wed, 11 Dec 2019 09:52:04 +0000 From: Xiaojun Liu To: "xiao.w.wang@intel.com" , "qi.z.zhang@intel.com" , "ngai-mint.kwan@intel.com" , "jakub.fornal@intel.co" , "jacob.e.keller@intel.com" CC: "dev@dpdk.org" , Xiaojun Liu Thread-Topic: [PATCH v2 2/7] net/fm10k: add some modules of port Thread-Index: AQHVsAikB062L+C/SkCac7TF7dPsAQ== Date: Wed, 11 Dec 2019 09:52:04 +0000 Message-ID: <1576057875-7677-3-git-send-email-xiaojun.liu@silicom.co.il> References: <1576057875-7677-1-git-send-email-xiaojun.liu@silicom.co.il> In-Reply-To: <1576057875-7677-1-git-send-email-xiaojun.liu@silicom.co.il> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR02CA0180.apcprd02.prod.outlook.com (2603:1096:201:21::16) To DB7PR04MB5196.eurprd04.prod.outlook.com (2603:10a6:10:1a::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=xiaojun.liu@silicom.co.il; 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x-microsoft-antispam-message-info: 27Kcppeo54AYrWKvlxO+hZ4o6uUJuMaRfFaHLE4Gxkm8d2y4bNlGYIhnzPXPOvVxBpZYQHqaTXcodegvwWQcVU4n8LiMR8i+ylCM/0sBQtT/WuB6EDZspdqFu63twddILC5bBYZNlSdthWcw6vgl2fWsl0CDi21/ULnlxxuY7Q44JpxBuXYVAqFvLikwARGJ/jbdS+ceIP9NShucwXmzLge+kfLI86ojcvXKAiPXlWKqgakxY+pykCfvhaFpIkPTJ42uY3V3xahg+h3os6B8AansYcuHqMY2zQZaL/WoZOIMXAKuCjnEVeevO1MufXQhwHSbuImj7a8K5AKXL4KLXYEzUj9VD5UrcFKn/+6Nx3Eh1GEqR3t9ALQ1dSq5bgpbSf2v67MJVP136o8nbAGpEb5GxxR8yMD9MJFkR0c+yfoxgrXUA3cIH9pQIRuBsXwJVeL4iyMKt6SW5AHFM5bio1ngKGYr6y65KoWjXVsLN3FMwWYqv32B1Mb7ED+o6f+O MIME-Version: 1.0 X-OriginatorOrg: silicom.co.il X-MS-Exchange-CrossTenant-Network-Message-Id: 6cf7bd1c-08dd-499f-c39e-08d77e1fc6ad X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Dec 2019 09:52:04.4173 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: c9e326d8-ce47-4930-8612-cc99d3c87ad1 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UwFplMHgsWbc/EbTJ+9CtR0z+impcVDSXIISphAj6gAh4oOFfnpz9ASrUV0kEuAvzpT8yk1C7b8zA1GOHV2q+0b4gM04qB8sC6bedgpwtro= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB5050 Subject: [dpdk-dev] [PATCH v2 2/7] net/fm10k: add some modules of port X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To support switch management, add the following new files: Add fm10k/switch/fm10k_spico_code.h. Add fm10k/switch/fm10k_spico_code.c(define spico code for serdes) Add fm10k/switch/fm10k_serdes.h Add fm10k/switch/fm10k_serdes.c(support serdes management) Add fm10k/switch/fm10k_sm.h Add fm10k/switch/fm10k_sm.c(state machine for external ports) Add fm10k/switch/fm10k_ext_port.h Add fm10k/switch/fm10k_ext_port.c(support external ports) and modify fm10k/Makefile(add fm10k_sm.c, fm10k_spico_code.c, fm10k_serdes.c and fm10k_ext_port.c). To avoid configuration for both kernel driver and userspace SDK outside DPDK, we add switch management in FM10K DPDK PMD driver. To enable switch management, you need add CONFIG_RTE_FM10K_MANAGEMENT=y in config/common_linux when building. Signed-off-by: Xiaojun Liu --- drivers/net/fm10k/Makefile | 4 + drivers/net/fm10k/switch/fm10k_ext_port.c | 841 ++++++++ drivers/net/fm10k/switch/fm10k_ext_port.h | 136 ++ drivers/net/fm10k/switch/fm10k_serdes.c | 1886 +++++++++++++++++ drivers/net/fm10k/switch/fm10k_serdes.h | 32 + drivers/net/fm10k/switch/fm10k_sm.c | 182 ++ drivers/net/fm10k/switch/fm10k_sm.h | 78 + drivers/net/fm10k/switch/fm10k_spico_code.c | 2966 +++++++++++++++++++++++++++ drivers/net/fm10k/switch/fm10k_spico_code.h | 21 + 9 files changed, 6146 insertions(+) create mode 100644 drivers/net/fm10k/switch/fm10k_ext_port.c create mode 100644 drivers/net/fm10k/switch/fm10k_ext_port.h create mode 100644 drivers/net/fm10k/switch/fm10k_serdes.c create mode 100644 drivers/net/fm10k/switch/fm10k_serdes.h create mode 100644 drivers/net/fm10k/switch/fm10k_sm.c create mode 100644 drivers/net/fm10k/switch/fm10k_sm.h create mode 100644 drivers/net/fm10k/switch/fm10k_spico_code.c create mode 100644 drivers/net/fm10k/switch/fm10k_spico_code.h diff --git a/drivers/net/fm10k/Makefile b/drivers/net/fm10k/Makefile index aca6bfb..4ec2a80 100644 --- a/drivers/net/fm10k/Makefile +++ b/drivers/net/fm10k/Makefile @@ -84,8 +84,12 @@ SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_vf.c SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_api.c ifeq ($(CONFIG_RTE_FM10K_MANAGEMENT),y) +SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_ext_port.c SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_i2c.c SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_sbus.c +SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_serdes.c +SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_sm.c +SRCS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k_spico_code.c endif SRCS-$(CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR) += fm10k_rxtx_vec.c diff --git a/drivers/net/fm10k/switch/fm10k_ext_port.c b/drivers/net/fm10k/switch/fm10k_ext_port.c new file mode 100644 index 0000000..e838fff --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_ext_port.c @@ -0,0 +1,841 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "fm10k_debug.h" +#include "fm10k_ext_port.h" +#include "fm10k_i2c.h" +#include "fm10k_regs.h" +#include "fm10k_serdes.h" +#include "fm10k_sm.h" +#include "fm10k_switch.h" + + +#define LANE_EVENT(e_) FM10K_SW_EXT_PORT_LANE_EVENT_##e_ +#define LANE_TIMER(t_) FM10K_SW_EXT_PORT_LANE_TIMER_##t_ +#define LANE_TIMEOUT(t_) FM10K_SW_EXT_PORT_LANE_##t_##_TIMEOUT_MS +#define LANE_POLL(t_) FM10K_SW_EXT_PORT_LANE_##t_##_POLL_MS +#define LANE_STATE(s_) FM10K_SW_EXT_PORT_LANE_STATE_##s_ +#define LANE_FLAG(f_) FM10K_SW_EXT_PORT_LANE_FLAG_##f_ +#define LANE_FLAGS(f_) FM10K_SW_EXT_PORT_LANE_FLAGS_##f_ +#define LANE_FLAG_SET(l_, f_) ((l_)->flags & LANE_FLAG(f_)) +#define LANE_FLAGS_SET(l_, f_, f1_) \ + (((l_)->flags & LANE_FLAGS(f_)) == LANE_FLAGS(f1_)) + +#define PORT_EVENT(e_) FM10K_SW_EXT_PORT_EVENT_##e_ +#define PORT_STATE(s_) FM10K_SW_EXT_PORT_STATE_##s_ + +static void fm10k_ext_ports_epl_intr + (struct fm10k_ext_ports *ports, unsigned int eplno); +static void fm10k_ext_port_intr(struct fm10k_ext_port *port, uint32_t epl_ip); +static void fm10k_ext_port_process_event(struct fm10k_sm *sm, uint16_t event); +static void fm10k_ext_port_bring_down(struct fm10k_ext_port *port); +static void fm10k_ext_port_lane_process_event + (struct fm10k_sm *sm, uint16_t event); +static void fm10k_ext_port_lane_process_timer + (struct fm10k_sm *sm, uint16_t timer); +static void fm10k_ext_port_restart_lane(struct fm10k_ext_port_lane *lane); +static void fm10k_ext_port_disable_lane(struct fm10k_ext_port_lane *lane); +static void fm10k_ext_port_phy_enable(struct fm10k_ext_port *port); +static void fm10k_ext_port_phy_disable(struct fm10k_ext_port *port); + +struct fm10k_ext_ports * +fm10k_ext_ports_attach(struct fm10k_switch *sw) +{ +// struct fm10k_pep *pep = sw->pep; + struct fm10k_ext_ports *ports; + struct fm10k_ext_port *port; + struct fm10k_ext_port_lane *lane; + struct fm10k_device_info *cfg = sw->info; + unsigned int is_quad, lane_speed; + unsigned int i, j; + unsigned int eplidx, laneno; + + FM10K_SW_TRACE("attaching external ports\n"); + + ports = (struct fm10k_ext_ports *)rte_zmalloc + ("fm10k_ext_ports", sizeof(struct fm10k_ext_ports), 0); + if (ports == NULL) { + FM10K_SW_ERR("failed to allocate external ports\n"); + goto fail; + } + + ports->ports = (struct fm10k_ext_port *)rte_zmalloc + ("fm10k_ext_port_list", + sizeof(struct fm10k_ext_port) * cfg->num_ext_ports, 0); + if (ports->ports == NULL) { + FM10K_SW_ERR("failed to allocate external ports list\n"); + goto fail; + } + ports->sw = sw; + ports->num_ports = cfg->num_ext_ports; + ports->ports_per_epl = cfg->num_ext_ports / cfg->num_epls; + ports->epl_mask = 0; + + switch (cfg->ext_port_speed) { + default: + case 10: + is_quad = 0; + lane_speed = 10; + break; + case 25: + is_quad = 0; + lane_speed = 25; + break; + case 40: + is_quad = 1; + lane_speed = 10; + break; + case 100: + is_quad = 1; + lane_speed = 25; + break; + } + + for (i = 0; i < ports->num_ports; i++) { + port = &ports->ports[i]; + port->ports = ports; + fm10k_ext_port_eplidx_lane(ports, i, &eplidx, &laneno); + port->portno = i; + port->eplno = fm10k_switch_eplidx_to_eplno(sw, eplidx); + snprintf(port->name, sizeof(port->name), "EPL[%u][%u]", + port->eplno, port->first_lane); + port->first_lane = laneno; + port->is_quad = is_quad; + port->num_lanes = port->is_quad ? 4 : 1; + port->lane_speed = lane_speed; + port->sm = fm10k_sm_attach + (FM10K_SW_EXT_PORT_NUM_EVENTS, 0, + fm10k_ext_port_process_event, NULL, + (void *)port); + if (port->sm == NULL) + goto fail; + port->sm->portno = port->portno; + port->sm->laneno = 0; + port->an_im = FM10K_SW_AN_IM_ALL; + port->link_im = FM10K_SW_LINK_IM_ALL; + + for (j = port->first_lane; + j < port->first_lane + port->num_lanes; j++) { + lane = &port->lanes[j]; + lane->port = port; + lane->abs_laneno = port->eplno * FM10K_SW_EPL_LANES + j; + lane->rel_laneno = j; + lane->im = FM10K_SW_SERDES_IM_ALL; + lane->sm = fm10k_sm_attach + (FM10K_SW_EXT_PORT_LANE_NUM_EVENTS, + FM10K_SW_EXT_PORT_LANE_NUM_TIMERS, + fm10k_ext_port_lane_process_event, + fm10k_ext_port_lane_process_timer, + (void *)lane); + if (lane->sm == NULL) + goto fail; + lane->sm->portno = lane->port->portno; + lane->sm->laneno = lane->rel_laneno; + } + + ports->epl_mask |= (1 << port->eplno); + } + + return (ports); +fail: + if (ports) + fm10k_ext_ports_detach(ports); + return NULL; +} + +void +fm10k_ext_ports_detach(struct fm10k_ext_ports *ports) +{ + struct fm10k_ext_port *port; + struct fm10k_ext_port_lane *lane; + unsigned int i, j; + + FM10K_SW_TRACE("detaching external ports\n"); + + if (ports->ports) { + for (i = 0; i < ports->num_ports; i++) { + port = &ports->ports[i]; + + if (port->sm) + fm10k_sm_detach(port->sm); + for (j = port->first_lane; + j < port->first_lane + port->num_lanes; j++) { + lane = &port->lanes[j]; + if (lane->sm) + fm10k_sm_detach(lane->sm); + } + + fm10k_ext_port_phy_disable(port); + } + rte_free(ports->ports); + } + + rte_free(ports); +} + +unsigned int +fm10k_ext_ports_epl_intrs(struct fm10k_ext_ports *ports, uint64_t gid) +{ + unsigned int i; + uint16_t epl_mask; + + /* + * Process EPL interrupts for all EPLs that are in use and have + * their bit set in global interrupt detect. + */ + epl_mask = ports->epl_mask & + FM10K_SW_REG_FIELD64(gid, GLOBAL_INTERRUPT_DETECT_EPL); + for (i = 0; i < FM10K_SW_EPLS_MAX; i++) + if (epl_mask & (1 << i)) + fm10k_ext_ports_epl_intr(ports, i); + + return ports->epl_mask; +} + +static void +fm10k_ext_ports_epl_intr(struct fm10k_ext_ports *ports, unsigned int eplno) +{ + struct fm10k_switch *sw = ports->sw; + struct fm10k_ext_port *port; + uint64_t gid; + unsigned int i, j; + uint32_t epl_ip; + + /* + * The global interrupt detect architecture makes it somewhat + * challenging to ensure events are not lost and spurious interrupts + * are not generated. + * + * The EPLs have an internal interrupt hierarchy whose reporting is + * rooted at EPL_IP. Whenever an EPL transitions from having no + * unmasked interrupts pending to at least one unmasked interrupt + * pending or from having at least one unmasked interrupt pending to + * no unmasked interrupts pending, it sends a vector to the + * interrupt controller over a serial bus indicating the + * at-least-one/none pending state, and the controller updates the + * bit for that EPL in the global interrupt detect register + * accordingly. + * + * Because of the update-vector-in-flight potential, there is a race + * between re-enabling the EPL PCIe interrupt mask after servicing + * the EPL interrupts and the all-clear vector from the EPL reaching + * the interrupt controller - it's possible for the software to + * clear all the EPL-internal interrupt sources during servicing and + * then re-enable the EPL interrupt in the PCIe mask before the + * all-clear vector reaches the interrupt controller and clears the + * EPL pending bit in the global interrupt detect register. This + * would result in a spurious EPL interrupt, potentially for every + * necessary EPL interrupt. + * + * The approach taken here to avoid spurious interrupts is to first + * mask off all EPL-internal sources, then poll the EPL bits in the + * global interrupt detect register until they clear (indicating the + * update vector from the EPL has reached the interrupt controller). + * Then software interrupt processing proceeds, and the EPL-internal + * masks are restored to their desired state at the end. This + * ensures that when the EPL PCIe interrupt mask is re-enabled, the + * EPL pending bits in the global interrupt detect register will + * only be set if there are new, unprocessed EPL events of interest. + * + */ + FM10K_SW_SWITCH_LOCK(sw); + /* Grab epl_ip before it is cleared by the masks below */ + epl_ip = fm10k_read_switch_reg(sw, FM10K_SW_EPL_IP(eplno)); + for (i = 0; i < ports->num_ports; i++) { + port = &ports->ports[i]; + if (port->eplno != eplno) + continue; + + fm10k_write_switch_reg(sw, + FM10K_SW_AN_IM(eplno, port->first_lane), + FM10K_SW_AN_IM_ALL); + fm10k_write_switch_reg(sw, + FM10K_SW_LINK_IM(eplno, port->first_lane), + FM10K_SW_LINK_IM_ALL); + + for (j = port->first_lane; + j < port->first_lane + port->num_lanes; j++) { + fm10k_write_switch_reg(sw, + FM10K_SW_SERDES_IM(eplno, j), + FM10K_SW_SERDES_IM_ALL); + } + } + + /* + * Wait for the all-clear vector to propagate over the internal + * interrupt serial bus to the global interrupt detect. + */ + do { + gid = fm10k_read_switch_reg64 + (sw, FM10K_SW_GLOBAL_INTERRUPT_DETECT); + } while (gid & FM10K_SW_GLOBAL_INTERRUPT_DETECT_EPL(eplno)); + FM10K_SW_SWITCH_UNLOCK(sw); + + /* + * Proceed with interrupt processing per-external-port. + */ + for (i = 0; i < ports->num_ports; i++) { + port = &ports->ports[i]; + if (port->eplno != eplno) + continue; + fm10k_ext_port_intr(port, epl_ip); + } +} + +static void +fm10k_ext_port_intr(struct fm10k_ext_port *port, uint32_t epl_ip) +{ + struct fm10k_switch *sw = port->ports->sw; + struct fm10k_ext_port_lane *lane; + unsigned int i; + uint32_t serdes_ip, data = 0; + + for (i = port->first_lane; + i < port->first_lane + port->num_lanes; i++) { + lane = &port->lanes[i]; + if (epl_ip & FM10K_SW_EPL_IP_SERDES_INTERRUPT(i)) { + FM10K_SW_SWITCH_LOCK(sw); + serdes_ip = fm10k_read_switch_reg(sw, + FM10K_SW_SERDES_IP(port->eplno, i)); + serdes_ip &= ~lane->im; + fm10k_write_switch_reg(sw, + FM10K_SW_SERDES_IP(port->eplno, i), serdes_ip); + if (serdes_ip & FM10K_SW_SERDES_IP_RX_SIGNAL_OK) + data = + fm10k_read_switch_reg(sw, + FM10K_SW_LANE_SERDES_STATUS(port->eplno, + i)); + FM10K_SW_SWITCH_UNLOCK(sw); + + if (serdes_ip & FM10K_SW_SERDES_IP_RX_SIGNAL_OK) { + fm10k_sm_send_event(lane->sm, + (data & + FM10K_SW_LANE_SERDES_STATUS_RX_SIGNAL_OK) ? + LANE_EVENT(SIGNAL_OK) : LANE_EVENT(SIGNAL_NOK)); + } + + if (serdes_ip & FM10K_SW_SERDES_IP_RX_RDY) + fm10k_sm_send_event(lane->sm, + LANE_EVENT(RX_PLL_LOCK)); + + if (serdes_ip & FM10K_SW_SERDES_IP_TX_RDY) + fm10k_sm_send_event(lane->sm, + LANE_EVENT(TX_PLL_LOCK)); + } else { + fm10k_sm_send_event(lane->sm, + LANE_EVENT(RESTORE_IM)); + } + } +} + +void +fm10k_ext_port_up(struct fm10k_ext_port *port) +{ + fm10k_sm_send_event(port->sm, PORT_EVENT(BRING_UP)); +} + +void +fm10k_ext_port_down(struct fm10k_ext_port *port) +{ + fm10k_sm_send_event(port->sm, PORT_EVENT(BRING_DOWN)); +} + +unsigned int +fm10k_ext_port_isup(struct fm10k_ext_port *port) +{ + /* no locked needed as we are just inspecting + * the current value of an int + */ + unsigned int port_state = port->sm->state; + + return (port_state == FM10K_SW_EXT_PORT_STATE_UP); +} + +static void +fm10k_ext_port_process_event(struct fm10k_sm *sm, uint16_t event) +{ + struct fm10k_ext_port *port = sm->ctx; + struct fm10k_ext_port_lane *lane; + unsigned int i; + unsigned int lanes_up; + + switch (sm->state) { + case PORT_STATE(DOWN): + if (event == PORT_EVENT(BRING_UP)) { + fm10k_ext_port_phy_enable(port); + + for (i = port->first_lane; + i < port->first_lane + port->num_lanes; i++) { + lane = &port->lanes[i]; + fm10k_sm_send_event + (lane->sm, LANE_EVENT(BRING_UP)); + } + sm->state = PORT_STATE(WAITING_FOR_LANES); + } + break; + + case PORT_STATE(WAITING_FOR_LANES): + if (event == PORT_EVENT(LANE_UP)) { + lanes_up = 0; + for (i = port->first_lane; + i < port->first_lane + port->num_lanes; i++) { + lane = &port->lanes[i]; + if (lane->sm->state != LANE_STATE(UP)) + break; + lanes_up++; + } + if (lanes_up == port->num_lanes) { + sm->state = PORT_STATE(UP); + FM10K_SW_INFO + ("Port %d is LINK UP", port->portno); + } + } else if (event == PORT_EVENT(BRING_DOWN)) { + fm10k_ext_port_bring_down(port); + } + break; + + case PORT_STATE(UP): + if (event == PORT_EVENT(LANE_DOWN)) { + sm->state = PORT_STATE(WAITING_FOR_LANES); + FM10K_SW_INFO("Port %d is LINK DOWN", port->portno); + } else if (event == PORT_EVENT(BRING_DOWN)) { + fm10k_ext_port_bring_down(port); + FM10K_SW_INFO("Port %d is LINK DOWN", port->portno); + } + } +} + +static void +fm10k_ext_port_bring_down(struct fm10k_ext_port *port) +{ + struct fm10k_sm *sm = port->sm; + struct fm10k_ext_port_lane *lane; + unsigned int i; + + sm->state = PORT_STATE(DOWN); + + fm10k_ext_port_phy_disable(port); + + for (i = port->first_lane; + i < port->first_lane + port->num_lanes; i++) { + lane = &port->lanes[i]; + fm10k_sm_send_event(lane->sm, LANE_EVENT(BRING_DOWN)); + } +} + +static void +fm10k_ext_port_lane_process_event(struct fm10k_sm *sm, uint16_t event) +{ + struct fm10k_ext_port_lane *lane = sm->ctx; + struct fm10k_ext_port *port = lane->port; + struct fm10k_switch *sw = lane->port->ports->sw; + int error; + + switch (sm->state) { + case LANE_STATE(DOWN): + if (event == LANE_EVENT(BRING_UP)) { + lane->flags &= ~LANE_FLAGS(PLLS_LOCKED); + + /* + * Clear all pending interrupts. + */ + FM10K_SW_SWITCH_LOCK(sw); + fm10k_write_switch_reg(sw, + FM10K_SW_SERDES_IP(port->eplno, lane->rel_laneno), + FM10K_SW_SERDES_IP_ALL); + FM10K_SW_SWITCH_UNLOCK(sw); + + error = fm10k_epl_serdes_start_bringup(lane); + if (error == 0) { + sm->state = LANE_STATE(WAIT_PLL_LOCK); + + /* + * Enable PLL lock interrupts. + */ + lane->im &= ~(FM10K_SW_SERDES_IM_RX_RDY | + FM10K_SW_SERDES_IM_TX_RDY); + } + } + break; + + case LANE_STATE(WAIT_PLL_LOCK): + if (event == LANE_EVENT(RX_PLL_LOCK) || + event == LANE_EVENT(TX_PLL_LOCK)) { + if (event == LANE_EVENT(RX_PLL_LOCK)) + lane->flags |= LANE_FLAG(RX_LOCKED); + if (event == LANE_EVENT(TX_PLL_LOCK)) + lane->flags |= LANE_FLAG(TX_LOCKED); + if (LANE_FLAGS_SET(lane, PLLS_LOCKED, PLLS_LOCKED)) { + error = fm10k_epl_serdes_continue_bringup(lane); + if (error == 0) { + sm->state = LANE_STATE(WAIT_SIGNAL_OK); + /* unmask RX signal OK interrupt */ + lane->im |= + (FM10K_SW_SERDES_IM_RX_RDY | + FM10K_SW_SERDES_IM_TX_RDY); + lane->im &= + ~FM10K_SW_SERDES_IM_RX_SIGNAL_OK; + } + } + } else if (event == LANE_EVENT(BRING_DOWN)) { + fm10k_ext_port_disable_lane(lane); + } + break; + + case LANE_STATE(WAIT_SIGNAL_OK): + if (event == LANE_EVENT(SIGNAL_OK)) { + sm->state = LANE_STATE(WAIT_DFE_ICAL); + + fm10k_epl_serdes_configure_for_dfe_tuning(lane); + fm10k_epl_serdes_start_dfe_ical(lane); + + lane->dfe_poll_time_ms = 0; + fm10k_sm_timer_start(sm, LANE_TIMER(DFE_TUNING), + LANE_POLL(DFE_ICAL)); + } else if (event == LANE_EVENT(BRING_DOWN)) { + fm10k_ext_port_disable_lane(lane); + } + break; + + case LANE_STATE(WAIT_DFE_ICAL): + if (event == LANE_EVENT(DFE_TUNING_COMPLETE)) { + sm->state = LANE_STATE(WAIT_DFE_PCAL); + + fm10k_epl_serdes_start_dfe_pcal(lane); + + lane->dfe_poll_time_ms = 0; + fm10k_sm_timer_start(sm, LANE_TIMER(DFE_TUNING), + LANE_POLL(DFE_PCAL)); + } else if ((event == LANE_EVENT(DFE_TUNING_FAILED)) || + (event == LANE_EVENT(DFE_TUNING_TIMED_OUT))) { + fm10k_ext_port_restart_lane(lane); + } else if (event == LANE_EVENT(BRING_DOWN)) { + fm10k_ext_port_disable_lane(lane); + } + break; + + case LANE_STATE(WAIT_DFE_PCAL): + if (event == LANE_EVENT(DFE_TUNING_COMPLETE)) { + fm10k_epl_serdes_set_signal_detect(lane, + FM10K_SW_LANE_OVERRIDE_NORMAL); + + sm->state = LANE_STATE(UP); + fm10k_sm_send_event(port->sm, PORT_EVENT(LANE_UP)); + } else if ((event == LANE_EVENT(DFE_TUNING_FAILED)) || + (event == LANE_EVENT(DFE_TUNING_TIMED_OUT)) || + (event == LANE_EVENT(SIGNAL_NOK))) { + fm10k_ext_port_restart_lane(lane); + } else if (event == LANE_EVENT(BRING_DOWN)) { + fm10k_ext_port_disable_lane(lane); + } + break; + + case LANE_STATE(UP): + if (event == LANE_EVENT(SIGNAL_NOK)) + fm10k_ext_port_restart_lane(lane); + else if (event == LANE_EVENT(BRING_DOWN)) + fm10k_ext_port_disable_lane(lane); + break; + } + + /* Always restore the interrupt mask */ + FM10K_SW_SWITCH_LOCK(sw); + fm10k_write_switch_reg(sw, + FM10K_SW_SERDES_IM(port->eplno, + lane->rel_laneno), + lane->im); + FM10K_SW_SWITCH_UNLOCK(sw); +} + +static void +fm10k_ext_port_lane_process_timer(struct fm10k_sm *sm, uint16_t timer) +{ + struct fm10k_ext_port_lane *lane = sm->ctx; + uint32_t status; + + switch (sm->state) { + case LANE_STATE(WAIT_DFE_ICAL): + if (timer == LANE_TIMER(DFE_TUNING)) { + lane->dfe_poll_time_ms += LANE_POLL(DFE_ICAL); + fm10k_epl_serdes_dfe_ical_status(lane, &status); + + if (status == FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS) { + if (lane->dfe_poll_time_ms < + LANE_TIMEOUT(DFE_ICAL)) + fm10k_sm_timer_start(sm, + LANE_TIMER(DFE_TUNING), + LANE_POLL(DFE_ICAL)); + else + fm10k_sm_send_event(sm, + LANE_EVENT(DFE_TUNING_TIMED_OUT)); + } else if (status == FM10K_SW_SERDES_DFE_ICAL_CONVERGED) + fm10k_sm_send_event(sm, + LANE_EVENT(DFE_TUNING_COMPLETE)); + else + fm10k_sm_send_event(sm, + LANE_EVENT(DFE_TUNING_FAILED)); + } + break; + + case LANE_STATE(WAIT_DFE_PCAL): + if (timer == LANE_TIMER(DFE_TUNING)) { + lane->dfe_poll_time_ms += LANE_POLL(DFE_PCAL); + + fm10k_epl_serdes_dfe_pcal_status(lane, &status); + if (status == FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS) { + if (lane->dfe_poll_time_ms < + LANE_TIMEOUT(DFE_PCAL)) + fm10k_sm_timer_start(sm, + LANE_TIMER(DFE_TUNING), + LANE_POLL(DFE_PCAL)); + else + fm10k_sm_send_event(sm, + LANE_EVENT(DFE_TUNING_TIMED_OUT)); + } else { + fm10k_sm_send_event(sm, + LANE_EVENT(DFE_TUNING_COMPLETE)); + } + } + break; + } +} + +static void +fm10k_ext_port_restart_lane(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_sm *sm = lane->sm; + struct fm10k_ext_port *port = lane->port; + int error; + + error = fm10k_epl_serdes_start_bringup(lane); + if (error == 0) { + sm->state = LANE_STATE(WAIT_PLL_LOCK); + + /* + * Enable PLL lock interrupts. + */ + lane->flags &= ~FM10K_SW_EXT_PORT_LANE_FLAGS_PLLS_LOCKED; + lane->im |= FM10K_SW_SERDES_IM_RX_SIGNAL_OK; + lane->im = ~(FM10K_SW_SERDES_IM_RX_RDY | + FM10K_SW_SERDES_IM_TX_RDY); + } + + fm10k_sm_send_event(port->sm, PORT_EVENT(LANE_DOWN)); +} + +static void +fm10k_ext_port_disable_lane(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_sm *sm = lane->sm; + + fm10k_sm_timer_cancel(sm, LANE_TIMER(DFE_TUNING)); + fm10k_epl_serdes_disable(lane); + + /* + * Disable all interrupts. + */ + lane->im = FM10K_SW_SERDES_IM_ALL; + + sm->state = LANE_STATE(DOWN); +} + +void +fm10k_ext_port_eplidx_lane(struct fm10k_ext_ports *ports, + unsigned int ext_port_idx, unsigned int *eplidx, + unsigned int *lane) +{ + FM10K_SW_ASSERT(ext_port_idx < ports->num_ports, + ("ext_port_idx out of range")); + + *eplidx = ext_port_idx / ports->ports_per_epl; + *lane = ext_port_idx % ports->ports_per_epl; +} + + +static void +fm10k_ext_port_phy_enable(struct fm10k_ext_port *port) +{ + struct fm10k_switch *sw = port->ports->sw; + struct fm10k_device_info *cfg = sw->info; + + switch (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice)) { + case FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS41): + case FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS41): + case FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS43): + case FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS43): + case FM10K_SW_CARD(SILICOM, PE340G2DBIR_QL4): + case FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QL4): + FM10K_SW_I2C_LOCK(sw->i2c); + /* Set up the first PCA9545 mux so we can get at the + * PCA9505 that the QSFP control lines are connected + * to. + */ + fm10k_i2c_write8(sw->i2c, 0x70, 0x04); + + /* Configure the I/O pins on the PCA9505 that are + * connected to LpMode and ResetL on the QSFP as + * outputs, and set LpMode to low to enable high + * power mode and set ResetL to high to take it out + * of reset. + */ + if (port->portno == 0) { + fm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x08); + } else { + fm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x08); + } + FM10K_SW_I2C_UNLOCK(sw->i2c); + break; + + case FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4): + case FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4_REV_2): + FM10K_SW_I2C_LOCK(sw->i2c); + /* Set up the first PCA9545 mux so we can get + * at the PCA9505 that the QSFP control lines + * are connected to. + */ + fm10k_i2c_write8(sw->i2c, 0x70, 0x01); + + /* Configure the I/O pins on the PCA9505 that are + * connected to LpMode and ResetL on the QSFP as + * outputs, and set LpMode to low to enable high + * power mode and set ResetL to high to take it out + * of reset. + */ + if (port->portno == 0) { + fm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x08); + } else { + fm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x08); + } + FM10K_SW_I2C_UNLOCK(sw->i2c); + break; + + case FM10K_SW_CARD(SILICOM, PE3100G2DQIRL_QXSL4): + case FM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4): + FM10K_SW_I2C_LOCK(sw->i2c); + + /* Configure the I/O pins on the PCA9538 that are + * connected to LpMode and ResetL on the QSFP as + * outputs, and set LpMode to low to enable high + * power mode and set ResetL to high to take it out + * of reset. + */ + if (port->portno == 0) { + fm10k_i2c_write16(sw->i2c, 0x60, 0x03, 0xcf); + fm10k_i2c_write16(sw->i2c, 0x60, 0x01, 0x10); + } else { + fm10k_i2c_write16(sw->i2c, 0x61, 0x03, 0xcf); + fm10k_i2c_write16(sw->i2c, 0x61, 0x01, 0x10); + } + FM10K_SW_I2C_UNLOCK(sw->i2c); + break; + + default: + FM10K_SW_ERR("don't know how to enable phy for this card " + "(subvendor=0x%04x subdevice=0x%04x)\n", + cfg->subvendor, cfg->subdevice); + break; + } +} + +static void +fm10k_ext_port_phy_disable(struct fm10k_ext_port *port) +{ + struct fm10k_switch *sw = port->ports->sw; + struct fm10k_device_info *cfg = sw->info; + + switch (FM10K_SW_CARD_ID(cfg->subvendor, cfg->subdevice)) { + case FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS41): + case FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS41): + case FM10K_SW_CARD(SILICOM, PE340G2DBIR_QS43): + case FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QS43): + case FM10K_SW_CARD(SILICOM, PE340G2DBIR_QL4): + case FM10K_SW_CARD(SILICOM_RB, PE340G2DBIR_QL4): + FM10K_SW_I2C_LOCK(sw->i2c); + /* Set up the first PCA9545 mux so we can get at the PCA9505 + * that the QSFP control lines are connected to. + */ + fm10k_i2c_write8(sw->i2c, 0x70, 0x04); + + /* Configure the I/O pins on the PCA9505 that are + * connected to LpMode and ResetL on the QSFP as + * outputs, and set LpMode to high to disable high + * power mode and set ResetL to low to put it in + * reset. + */ + if (port->portno == 0) { + fm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x01); + } else { + fm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x01); + } + FM10K_SW_I2C_UNLOCK(sw->i2c); + break; + + case FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4): + case FM10K_SW_CARD(SILICOM, PE3100G2DQIR_QXSL4_REV_2): + FM10K_SW_I2C_LOCK(sw->i2c); + /* Set up the first PCA9545 mux so we can get at the PCA9505 + * that the QSFP control lines are connected to. + */ + fm10k_i2c_write8(sw->i2c, 0x70, 0x01); + + /* Configure the I/O pins on the PCA9505 that are + * connected to LpMode and ResetL on the QSFP as + * outputs, and set LpMode to high to disable high + * power mode and set ResetL to low to put it in + * reset. + */ + if (port->portno == 0) { + fm10k_i2c_write16(sw->i2c, 0x20, 0x18, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x08, 0x01); + } else { + fm10k_i2c_write16(sw->i2c, 0x20, 0x19, 0xf6); + fm10k_i2c_write16(sw->i2c, 0x20, 0x09, 0x01); + } + FM10K_SW_I2C_UNLOCK(sw->i2c); + break; + case FM10K_SW_CARD(SILICOM, PE3100G2DQIRL_QXSL4): + case FM10K_SW_CARD(SILICOM, PE3100G2DQIRM_QXSL4): + FM10K_SW_I2C_LOCK(sw->i2c); + /* Configure the I/O pins on the PCA9538 that are + * connected to LpMode and ResetL on the QSFP as + * outputs, and set LpMode to high to disable high + * power mode and set ResetL to low to put it in + * reset. + */ + if (port->portno == 0) { + fm10k_i2c_write16(sw->i2c, 0x60, 0x03, 0xcf); + fm10k_i2c_write16(sw->i2c, 0x60, 0x01, 0x20); + FM10K_SW_ERR("%s config PCA9538 %#x set LpMode", + __func__, 0x60); + } else { + fm10k_i2c_write16(sw->i2c, 0x61, 0x03, 0xcf); + fm10k_i2c_write16(sw->i2c, 0x61, 0x01, 0x20); + FM10K_SW_ERR("%s config PCA9538 %#x set LpMode", + __func__, 0x61); + } + FM10K_SW_I2C_UNLOCK(sw->i2c); + break; + + default: + FM10K_SW_ERR("don't know how to disable phy for this card " + "(subvendor=0x%04x subdevice=0x%04x)\n", + cfg->subvendor, cfg->subdevice); + break; + } +} diff --git a/drivers/net/fm10k/switch/fm10k_ext_port.h b/drivers/net/fm10k/switch/fm10k_ext_port.h new file mode 100644 index 0000000..7b0e94f --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_ext_port.h @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_SW_EXT_PORT_H_ +#define _FM10K_SW_EXT_PORT_H_ + +#include "fm10k_regs.h" +#include "fm10k_sm.h" +#include "fm10k_sbus.h" +#include "fm10k_switch.h" + + +struct fm10k_sbus; +struct fm10k_switch; + +#define FM10K_SW_TRACE_ENABLE 0 + +enum fm10k_ext_port_lane_state { + FM10K_SW_EXT_PORT_LANE_STATE_DOWN, + FM10K_SW_EXT_PORT_LANE_STATE_WAIT_PLL_LOCK, + FM10K_SW_EXT_PORT_LANE_STATE_WAIT_SIGNAL_OK, + FM10K_SW_EXT_PORT_LANE_STATE_WAIT_DFE_ICAL, + FM10K_SW_EXT_PORT_LANE_STATE_WAIT_DFE_PCAL, + FM10K_SW_EXT_PORT_LANE_STATE_UP +}; + +enum fm10k_ext_port_lane_event { + FM10K_SW_EXT_PORT_LANE_EVENT_BRING_UP, + FM10K_SW_EXT_PORT_LANE_EVENT_RX_PLL_LOCK, + FM10K_SW_EXT_PORT_LANE_EVENT_TX_PLL_LOCK, + FM10K_SW_EXT_PORT_LANE_EVENT_SIGNAL_OK, + FM10K_SW_EXT_PORT_LANE_EVENT_SIGNAL_NOK, + FM10K_SW_EXT_PORT_LANE_EVENT_DFE_TUNING_COMPLETE, + FM10K_SW_EXT_PORT_LANE_EVENT_DFE_TUNING_FAILED, + FM10K_SW_EXT_PORT_LANE_EVENT_DFE_TUNING_TIMED_OUT, + FM10K_SW_EXT_PORT_LANE_EVENT_RESTORE_IM, + FM10K_SW_EXT_PORT_LANE_EVENT_BRING_DOWN, + + FM10K_SW_EXT_PORT_LANE_NUM_EVENTS +}; + +enum fm10k_ext_port_lane_timer { + FM10K_SW_EXT_PORT_LANE_TIMER_PLL_LOCK, + FM10K_SW_EXT_PORT_LANE_TIMER_SIGNAL_OK, + FM10K_SW_EXT_PORT_LANE_TIMER_DFE_TUNING, + + FM10K_SW_EXT_PORT_LANE_NUM_TIMERS +}; + +#define FM10K_SW_EXT_PORT_LANE_PLL_LOCK_TIMEOUT_MS 2000 +#define FM10K_SW_EXT_PORT_LANE_SIGNAL_OK_TIMEOUT_MS 2000 +#define FM10K_SW_EXT_PORT_LANE_DFE_ICAL_POLL_MS 200 +#define FM10K_SW_EXT_PORT_LANE_DFE_ICAL_TIMEOUT_MS 3000 +#define FM10K_SW_EXT_PORT_LANE_DFE_PCAL_POLL_MS 100 +#define FM10K_SW_EXT_PORT_LANE_DFE_PCAL_TIMEOUT_MS 2000 + + +enum fm10k_ext_port_state { + FM10K_SW_EXT_PORT_STATE_DOWN, + FM10K_SW_EXT_PORT_STATE_WAITING_FOR_LANES, + FM10K_SW_EXT_PORT_STATE_UP +}; + +enum fm10k_ext_port_event { + FM10K_SW_EXT_PORT_EVENT_BRING_UP, + FM10K_SW_EXT_PORT_EVENT_BRING_DOWN, + FM10K_SW_EXT_PORT_EVENT_LANE_UP, + FM10K_SW_EXT_PORT_EVENT_LANE_DOWN, + + FM10K_SW_EXT_PORT_NUM_EVENTS +}; + +struct fm10k_ext_port; + +struct fm10k_ext_port_lane { + struct fm10k_ext_port *port; + struct fm10k_sm *sm; + uint32_t im; + uint16_t dfe_poll_time_ms; + uint8_t abs_laneno; + uint8_t rel_laneno; + uint8_t flags; +}; + +#define FM10K_SW_EXT_PORT_LANE_FLAG_RX_LOCKED 0x01 +#define FM10K_SW_EXT_PORT_LANE_FLAG_TX_LOCKED 0x02 + +#define FM10K_SW_EXT_PORT_LANE_FLAGS_PLLS_LOCKED \ + (FM10K_SW_EXT_PORT_LANE_FLAG_RX_LOCKED | \ + FM10K_SW_EXT_PORT_LANE_FLAG_TX_LOCKED) + +struct fm10k_ext_ports; + +struct fm10k_ext_port { + struct fm10k_ext_ports *ports; + struct fm10k_sm *sm; + struct fm10k_ext_port_lane lanes[FM10K_SW_EPL_LANES]; + char name[10]; + uint8_t portno; + uint8_t eplno; + uint8_t lport; /* filled in by switch */ + uint8_t first_lane; /* range is [0..3] */ + uint8_t num_lanes; + uint8_t is_quad; + uint8_t lane_speed; + uint8_t last_led_flags; + uint32_t an_im; + uint32_t link_im; +}; + +#define FM10K_SW_EXT_PORT_LED_FLAG_UP 0x01 +#define FM10K_SW_EXT_PORT_LED_FLAG_ACTIVE 0x02 + +struct fm10k_ext_ports { + struct fm10k_switch *sw; + struct fm10k_ext_port *ports; + uint16_t epl_mask; + uint8_t num_ports; + uint8_t ports_per_epl; +}; + +#define FM10K_SW_EXT_PORTS_EPL_USED(p_, n_) ((p_)->epl_mask & (1 << (n_))) + +struct fm10k_ext_ports *fm10k_ext_ports_attach(struct fm10k_switch *sw); +void fm10k_ext_ports_detach(struct fm10k_ext_ports *ports); +unsigned int fm10k_ext_ports_epl_intrs(struct fm10k_ext_ports *ports, + uint64_t gid); +void fm10k_ext_port_up(struct fm10k_ext_port *port); +void fm10k_ext_port_down(struct fm10k_ext_port *port); +unsigned int fm10k_ext_port_isup(struct fm10k_ext_port *port); +void fm10k_ext_port_eplidx_lane(struct fm10k_ext_ports *ports, + unsigned int ext_port_idx, unsigned int *eplidx, + unsigned int *lane); + +#endif /* _FM10K_SW_EXT_PORT_H_ */ diff --git a/drivers/net/fm10k/switch/fm10k_serdes.c b/drivers/net/fm10k/switch/fm10k_serdes.c new file mode 100644 index 0000000..8f4f2c6 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_serdes.c @@ -0,0 +1,1886 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#include +#include +#include +#include +#include +#include + +#include "fm10k_debug.h" +#include "fm10k_ext_port.h" +#include "fm10k_regs.h" +#include "fm10k_sbus.h" +#include "fm10k_serdes.h" +#include "fm10k_spico_code.h" +#include "fm10k_switch.h" + + +#define FM10K_SW_SERDES_BIST_TIMEOUT_MS 5000 +#define FM10K_SW_SBM_INTERRUPT_TIMEOUT_MS 5000 +#define FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS 3000 +#define FM10K_SW_SERDES_INT02_TIMEOUT_MS 500 + +#define FM10K_SW_SERDES_CONFIG_DELAY_US 20 +#define FM10K_SW_SERDES_RESET_DELAY_US 22 +#define FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US 200 + +#define FM10K_SW_SERDES_DIVIDER_ETHMODE_25G 0xa5 +#define FM10K_SW_SERDES_DIVIDER_ETHMODE_10G 0x42 + +#define FM10K_SW_SERDES_WIDTH_40 3 /* 25G */ +#define FM10K_SW_SERDES_WIDTH_20 1 /* 10G */ + +#define FM10K_SW_SERDES_EQ_SEL_PRECUR 0 +#define FM10K_SW_SERDES_EQ_SEL_ATTEN 1 +#define FM10K_SW_SERDES_EQ_SEL_POSTCUR 2 + +#define FM10K_SW_SERDES_DFE_DEFAULT_HF 0x00 +#define FM10K_SW_SERDES_DFE_DEFAULT_LF 0x0c +#define FM10K_SW_SERDES_DFE_DEFAULT_DC 0x38 +#define FM10K_SW_SERDES_DFE_DEFAULT_BW 0x0f + +#define FM10K_SW_SERDES_ICAL_STOP_MAX_CYCLES 10 +#define FM10K_SW_SERDES_PCAL_STOP_MAX_CYCLES 500 + +/* + * These values correspond to IES FM_PORT_LINK_OPTIMIZATION_BALANCE + * settings. + */ +#define FM10K_SW_LINK_OPT_PARAM_A10G 0x4800 +#define FM10K_SW_LINK_OPT_PARAM_B10G 0xA000 +#define FM10K_SW_LINK_OPT_PARAM_A25G 0x10001 +#define FM10K_SW_LINK_OPT_PARAM_B25G 0x10001 + +#define FM10K_SW_SERDES_DFE_DATA_LEVEL0_THRESHOLD 10 + + +static int fm10k_spico_ram_bist(struct fm10k_sbus *sb); +static int fm10k_load_epl_spico_code(struct fm10k_switch *sw); +static int fm10k_sbm_spico_upload_image(struct fm10k_sbus *sb, + const uint16_t *image, unsigned int num_words); +static int fm10k_sbm_check_crc_version_build_id(struct fm10k_sbus *sb, + uint32_t expected_version_build_id); +static int fm10k_sbm_spico_do_crc(struct fm10k_sbus *sb); +static int fm10k_sbm_get_version_build_id(struct fm10k_sbus *sb, + uint32_t *version_build_id); +static int fm10k_serdes_swap_upload_image(struct fm10k_sbus *sb, + const uint16_t *image, unsigned int num_words); +static int fm10k_serdes_swap_alt_upload_image(struct fm10k_sbus *sb, + const uint16_t *image, unsigned int num_words); +static int fm10k_swap_image_check_crc(struct fm10k_sbus *sb, + unsigned int crc_code); +static int fm10k_serdes_spico_upload_image(struct fm10k_sbus *sb, + uint8_t dev, const uint16_t *image, unsigned int num_words); +static int fm10k_epl_serdes_check_crc_version_build_id(struct fm10k_switch *sw, + uint32_t expected_version_build_id); +static int fm10k_epl_serdes_spico_do_crc(struct fm10k_switch *sw, + unsigned int serdes); +static int fm10k_epl_serdes_spico_reset(struct fm10k_switch *sw, + unsigned int serdes); +static int fm10k_epl_serdes_get_version_build_id(struct fm10k_switch *sw, + unsigned int serdes, uint32_t *version_build_id); +static int fm10k_sbm_spico_int(struct fm10k_sbus *sb, + uint8_t int_num, uint32_t param, uint32_t *result); +static int fm10k_epl_serdes_spico_int(struct fm10k_switch *sw, + unsigned int serdes, uint16_t int_num, + uint32_t param, uint32_t *result); +static int fm10k_epl_serdes_set_bit_rate(struct fm10k_switch *sw, + unsigned int serdes, unsigned int divider); +static int fm10k_epl_serdes_set_width_mode(struct fm10k_switch *sw, + unsigned int serdes, unsigned int width_mode); +static void fm10k_epl_serdes_set_pcsl_width_mode(struct fm10k_switch *sw, + unsigned int serdes, unsigned int width_mode); +static int fm10k_epl_serdes_set_pcsl_bit_slip(struct fm10k_switch *sw, + unsigned int serdes); +static int fm10k_epl_serdes_init_signal_ok(struct fm10k_switch *sw, + unsigned int serdes, unsigned int threshold); +static int fm10k_epl_serdes_set_tx_eq(struct fm10k_switch *sw, + unsigned int serdes, unsigned int which, unsigned int tx_eq); +static int fm10k_epl_serdes_spico_int02_retry(struct fm10k_switch *sw, + unsigned int serdes, uint32_t data, unsigned int timeout_ms); +static int fm10k_epl_serdes_dma_reg_write(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, uint32_t data); +static int fm10k_epl_serdes_dma_esb_write(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, uint32_t data); +static int fm10k_epl_serdes_dma_esb_read_modify_write(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, uint32_t data, + uint32_t mask, uint32_t *result); +static int fm10k_epl_serdes_dma_esb_read(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, uint32_t *result); +static int fm10k_epl_serdes_spico_wr_only_int(struct fm10k_switch *sw, + unsigned int serdes, unsigned int int_num, uint32_t param); +static void fm10k_epl_serdes_eplno_lane(struct fm10k_switch *sw, + unsigned int serdes, unsigned int *eplno, unsigned int *lane); +static int fm10k_epl_serdes_configure_near_loopback + (struct fm10k_ext_port_lane *lane); +static int fm10k_epl_serdes_config_dfe_param(struct fm10k_switch *sw, + unsigned int serdes, uint32_t param); +static int fm10k_epl_serdes_get_dfe_status(struct fm10k_switch *sw, + unsigned int serdes, uint32_t *status); +static int fm10k_epl_serdes_get_ical_result(struct fm10k_switch *sw, + unsigned int serdes, uint32_t *converged); + + +int +fm10k_epl_serdes_reset_and_load_all(struct fm10k_switch *sw) +{ + struct fm10k_sbus *sb = sw->epl_sbus; + int error; + + FM10K_SW_TRACE("sbus %s: initializing EPL serdes", sb->name); + + error = fm10k_spico_ram_bist(sb); + if (error) + goto done; + + error = fm10k_load_epl_spico_code(sw); + if (error) + goto done; + +done: + return (error); +} + +int +fm10k_spico_ram_bist(struct fm10k_sbus *sb) +{ + uint64_t start_time_us, elapsed_time_ms; + uint32_t data; + int error; + + FM10K_SW_TRACE("sbus %s: starting SPICO RAM BIST", sb->name); + + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x00, 0x03); + if (error) + goto done; + + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x00, 0x05); + if (error) + goto done; + + start_time_us = fm10k_uptime_us(); + elapsed_time_ms = 0; + while (elapsed_time_ms < FM10K_SW_SERDES_BIST_TIMEOUT_MS) { + elapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000; + error = fm10k_sbus_read(sb, + FM10K_SW_SBUS_ADDR_SPICO, 0x00, &data); + if (error) + goto done; + + if (data & 0x18) { + error = fm10k_sbus_write(sb, + FM10K_SW_SBUS_ADDR_SPICO, 0x00, 0x00); + if (error) + goto done; + if ((data & 0x18) != 0x08) { + FM10K_SW_INFO("sbus %s: SPICO RAM " + "BIST failed with bad status (0x%08x)", + sb->name, data); + error = -1; + goto done; + } + goto done; + } + } + fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x00, 0x00); + error = -1; + FM10K_SW_INFO("sbus %s: SPICO RAM BIST timed out after %u " + "ms", sb->name, (uint32_t)elapsed_time_ms); + +done: + return (error); +} + +static int +fm10k_load_epl_spico_code(struct fm10k_switch *sw) +{ + struct fm10k_sbus *sb = sw->epl_sbus; + const uint16_t *sbm_code_image; + uint32_t sbm_code_size; + uint32_t sbm_code_version_build_id; + const uint16_t *serdes_code_image; + uint32_t serdes_code_size; + uint32_t serdes_code_version_build_id; + const uint16_t *swap_code_image; + uint32_t swap_code_size; + unsigned int swap_crc_code; + int error = 0; + + FM10K_SW_TRACE("sbus %s: loading SPICO code", sb->name); + + sbm_code_image = fm10000_sbus_master_code_prd; + sbm_code_size = fm10000_sbus_master_code_size_prd; + sbm_code_version_build_id = + fm10000_sbus_master_code_version_build_id_prd; + + FM10K_SW_TRACE("sbus %s: sbm code version=%4.4x build=%4.4x", + sb->name, sbm_code_version_build_id >> 16, + sbm_code_version_build_id & 0xffff); + + serdes_code_image = fm10000_serdes_spico_code_prd2; + serdes_code_size = fm10000_serdes_spico_code_size_prd2; + serdes_code_version_build_id = + fm10000_serdes_spico_code_version_build_id_prd2; + sw->epl_serdes_code_version_build_id = serdes_code_version_build_id; + + FM10K_SW_TRACE("sbus %s: serdes code version=%4.4x build=%4.4x", + sb->name, serdes_code_version_build_id >> 16, + serdes_code_version_build_id & 0xffff); + + swap_code_image = fm10000_serdes_swap_code_prd2; + swap_code_size = fm10000_serdes_swap_code_size_prd2; + + error = fm10k_sbm_spico_upload_image(sb, sbm_code_image, + sbm_code_size); + if (error) + goto done; + + error = fm10k_sbm_check_crc_version_build_id(sb, + sbm_code_version_build_id); + if (error) + goto done; + + if (swap_code_size > 0) { + if ((sbm_code_version_build_id & 0x00008000) == 0) { + error = fm10k_serdes_swap_upload_image(sb, + swap_code_image, swap_code_size); + swap_crc_code = 0x1a; + } else { + error = fm10k_serdes_swap_alt_upload_image(sb, + swap_code_image, swap_code_size); + swap_crc_code = 0x04; + } + if (error) + goto done; + + error = fm10k_swap_image_check_crc(sb, swap_crc_code); + if (error) + goto done; + } + + error = fm10k_serdes_spico_upload_image(sb, + FM10K_SW_SBUS_ADDR_BROADCAST, + serdes_code_image, serdes_code_size); + if (error) + goto done; + + error = fm10k_epl_serdes_check_crc_version_build_id(sw, + serdes_code_version_build_id); + if (error) + goto done; + +done: + return (error); +} + + +static int +fm10k_sbm_spico_upload_image(struct fm10k_sbus *sb, + const uint16_t *image, unsigned int num_words) +{ + uint64_t start_time_us, elapsed_time_us; + unsigned int i; + uint32_t data; + int error; + + FM10K_SW_TRACE("sbus %s: uploading SBM SPICO image " + "(%u words)", sb->name, num_words); + + data = (1 << 6) | (1 << 7); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, data); + if (error) + goto done; + + data &= ~(1 << 7); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, data); + if (error) + goto done; + + data |= (1 << 9); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, data); + if (error) + goto done; + + start_time_us = fm10k_uptime_us(); + for (i = 0; i < num_words; i++) { + data = 0x80000000 | ((uint32_t)image[i] << 16) | i; + error = fm10k_sbus_write(sb, + FM10K_SW_SBUS_ADDR_SPICO, 0x03, data); + if (error) + goto done; + } + elapsed_time_us = fm10k_uptime_us() - start_time_us; + FM10K_SW_TRACE("sbus %s: SBM image upload time %u ms", + sb->name, (uint32_t)(elapsed_time_us / 1000)); + + data = (1 << 6); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, data); + if (error) + goto done; + + data = (1 << 18) | (1 << 19); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x16, data); + if (error) + goto done; + + data = (1 << 6) | (1 << 8); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, data); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_sbm_check_crc_version_build_id(struct fm10k_sbus *sb, + uint32_t expected_version_build_id) +{ + int error; + uint32_t version_build_id; + + FM10K_SW_TRACE("sbus %s: checking SBM SPICO code CRC " + "and version", sb->name); + + error = fm10k_sbm_spico_do_crc(sb); + if (error) + goto done; + + error = fm10k_sbm_get_version_build_id(sb, &version_build_id); + if (error) + goto done; + + if (version_build_id != expected_version_build_id) { + FM10K_SW_INFO("sbus %s: SBM SPICO code version " + "compare failed (expected 0x%08x, got 0x%08x)", + sb->name, expected_version_build_id, version_build_id); + error = -1; + goto done; + } + FM10K_SW_TRACE("sbus %s: SBM SPICO image " + "version=0x%4.4x build_id=0x%4.4x", sb->name, + version_build_id >> 16, + version_build_id & 0xffff); +done: + return (error); +} + +static int +fm10k_sbm_spico_do_crc(struct fm10k_sbus *sb) +{ + int error; + uint32_t crc; + + FM10K_SW_TRACE("sbus %s: performing SBM SPICO CRC " + "check", sb->name); + + error = fm10k_sbm_spico_int(sb, 0x02, 0, &crc); + if (error) + goto done; + + crc = crc >> 16; + if (crc == 0xffff) { + FM10K_SW_INFO("sbus %s: SBM SPICO CRC check failed " + "(CRC interrupt returned 0xffff)", sb->name); + error = -1; + goto done; + } else if (crc == 0x0001) + FM10K_SW_TRACE("sbus %s: SBM SPICO CRC check " + "passed ", sb->name); + else + FM10K_SW_INFO("sbus %s: unexpected SBM SPICO CRC " + "check result 0x%04x", sb->name, crc); + +done: + return (error); +} + +static int +fm10k_sbm_get_version_build_id(struct fm10k_sbus *sb, + uint32_t *version_build_id) +{ + int error; + uint32_t result; + + FM10K_SW_TRACE("sbus %s: getting SBM code version", + sb->name); + + error = fm10k_sbm_spico_int(sb, 0x00, 0, &result); + if (error) + goto done; + + *version_build_id = result & 0xffff0000; + error = fm10k_sbm_spico_int(sb, 0x01, 0, &result); + if (error) + goto done; + + *version_build_id |= (result >> 16) & 0xffff; + +done: + return (error); +} + +static int +fm10k_serdes_swap_upload_image(struct fm10k_sbus *sb, + const uint16_t *image, unsigned int num_words) +{ + uint64_t start_time_us, elapsed_time_us; + unsigned int i; + uint32_t addr; + uint32_t reg01, reg05; + int error; + + FM10K_SW_TRACE("sbus %s: uploading SBM swap image " + "(%u words)", sb->name, num_words); + + error = fm10k_sbm_spico_int(sb, 0x1c, 0, &addr); + if (error) + goto done; + + addr >>= 16; + if (addr == 0xffff) { + FM10K_SW_INFO("sbus %s: invalid build - cannot " + "upload SBM swap image", sb->name); + error = -1; + goto done; + } + FM10K_SW_TRACE("sbus %s: SBM swap image initial load " + "address 0x%04x (%u)", sb->name, addr, addr); + + reg05 = 1; + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x05, reg05); + if (error) + goto done; + + error = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, ®01); + if (error) + goto done; + + reg01 |= (1 << 9); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, reg01); + if (error) + goto done; + + start_time_us = fm10k_uptime_us(); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x03, addr); + if (error) + goto done; + error = fm10k_sbus_write(sb, + FM10K_SW_SBUS_ADDR_SPICO, 0x03, 0x80000000 | addr); + if (error) + goto done; + + for (i = 0; i < num_words - 2; i += 3) { + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x14, + 0xc0000000 | + image[i] | + ((uint32_t)image[i + 1] << 10) | + ((uint32_t)image[i + 2] << 20)); + if (error) + goto done; + } + + if (num_words - i == 2) { + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x14, + 0x80000000 | image[i] | ((uint32_t)image[i + 1] << 10)); + if (error) + goto done; + } else if (num_words - i == 1) { + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x14, + 0x40000000 | image[i]); + if (error) + goto done; + } + elapsed_time_us = fm10k_uptime_us() - start_time_us; + FM10K_SW_TRACE("sbus %s: SBM swap image upload time " + "%u ms", sb->name, (uint32_t)(elapsed_time_us / 1000)); + + reg01 &= ~(1 << 9); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, reg01); + if (error) + goto done; + + reg05 &= ~(1 << 0); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x05, reg05); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_serdes_swap_alt_upload_image(struct fm10k_sbus *sb, + const uint16_t *image, unsigned int num_words) +{ + uint64_t start_time_us, elapsed_time_us; + unsigned int i; + uint32_t addr; + uint32_t reg01, reg05; + int error; + + FM10K_SW_TRACE("sbus %s: alt-uploading SBM swap image " + "(%u words)", sb->name, num_words); + + reg05 = 1; + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x05, reg05); + if (error) + goto done; + + error = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, ®01); + if (error) + goto done; + + reg01 |= (1 << 10) | (1 << 11); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, reg01); + if (error) + goto done; + + addr = 0x0400; + FM10K_SW_TRACE("sbus %s: SBM swap image initial load " + "address 0x%04x (%u)", sb->name, addr, addr); + + start_time_us = fm10k_uptime_us(); + for (i = 0; i < num_words; i++) { + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x04, + 0x8000 | + ((uint32_t)image[i + 1] << 16) | + (addr + i)); + if (error) + goto done; + } + elapsed_time_us = fm10k_uptime_us() - start_time_us; + FM10K_SW_TRACE("sbus %s: SBM swap image alt-upload " + "time %u ms", sb->name, (uint32_t)(elapsed_time_us / 1000)); + + reg01 &= ~((1 << 10) | (1 << 11)); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x01, reg01); + if (error) + goto done; + + reg05 &= ~(1 << 0); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x05, reg05); + if (error) + goto done; + +done: + return error; +} + +static int +fm10k_swap_image_check_crc(struct fm10k_sbus *sb, unsigned int crc_code) +{ + int error; + uint32_t crc; + + FM10K_SW_TRACE("sbus %s: performing SBM swap image CRC " + "check", sb->name); + + error = + fm10k_sbm_spico_int(sb, crc_code, 0, &crc); + if (error) + goto done; + + crc >>= 16; + if (crc == 0xffff) { + FM10K_SW_INFO("sbus %s: SBM swap image CRC check " + "failed (CRC interrupt 0x%02x returned 0xffff)", + sb->name, crc_code); + error = -1; + goto done; + } else if (crc == 0x0001) + FM10K_SW_TRACE("sbus %s: SBM swap image CRC " + "check passed ", sb->name); + else + FM10K_SW_INFO("sbus %s: unexpected SBM swap image " + "CRC check result 0x%04x", sb->name, crc); + +done: + return (error); +} + +static int +fm10k_serdes_spico_upload_image(struct fm10k_sbus *sb, + uint8_t dev, const uint16_t *image, unsigned int num_words) +{ + uint64_t start_time_us, elapsed_time_us; + unsigned int i; + uint32_t data; + uint32_t reg07; + int error; + + FM10K_SW_TRACE("sbus %s: uploading serdes SPICO image " + "to bus address 0x%02x (%u words)", sb->name, dev, num_words); + + reg07 = (1 << 0) | (1 << 4); + error = fm10k_sbus_write(sb, dev, 0x07, reg07); + if (error) + goto done; + + reg07 &= ~(1 << 0); + error = fm10k_sbus_write(sb, dev, 0x07, reg07); + if (error) + goto done; + + data = (1 << 30); + error = fm10k_sbus_write(sb, dev, 0x00, data); + if (error) + goto done; + + data = (1 << 4) | (1 << 5); + error = fm10k_sbus_write(sb, dev, 0x08, data); + if (error) + goto done; + + start_time_us = fm10k_uptime_us(); + for (i = 0; i < num_words; i += 3) { + data = 0xc0000000 | image[i]; + if (i + 1 < num_words) { + data |= (uint32_t)image[i + 1] << 10; + + if (i + 2 < num_words) + data |= (uint32_t)image[i + 2] << 20; + } + error = fm10k_sbus_write(sb, dev, 0x0a, data); + if (error) + goto done; + } + elapsed_time_us = fm10k_uptime_us() - start_time_us; + FM10K_SW_TRACE("sbus %s: serdes SPICO image upload " + "time %u ms", sb->name, (uint32_t)(elapsed_time_us / 1000)); + + error = fm10k_sbus_write(sb, dev, 0x00, 0); + if (error) + goto done; + + error = fm10k_sbus_write(sb, dev, 0x01, 0x20000000); + if (error) + goto done; + + data = (1 << 18) | (1 << 19); + error = fm10k_sbus_write(sb, dev, 0x0b, data); + if (error) + goto done; + + reg07 |= (1 << 0); + error = fm10k_sbus_write(sb, dev, 0x07, reg07); + if (error) + goto done; + + reg07 &= ~(1 << 0); + error = fm10k_sbus_write(sb, dev, 0x07, reg07); + if (error) + goto done; + + reg07 |= (1 << 1); + error = fm10k_sbus_write(sb, dev, 0x07, reg07); + if (error) + goto done; + + error = fm10k_sbus_write(sb, dev, 0x08, 0); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_check_crc_version_build_id(struct fm10k_switch *sw, + uint32_t expected_version_build_id) +{ + struct fm10k_sbus *sb = sw->epl_sbus; + unsigned int first = 0; + unsigned int last = FM10K_SW_EPLS_MAX * FM10K_SW_EPL_LANES - 1; + unsigned int i; + int error; + uint32_t data; + uint32_t version_build_id; + + FM10K_SW_TRACE("sbus %s: checking SPICO code CRC and " + "version for serdes %u through %u", sb->name, first, last); + + for (i = first; i <= last; i++) { + error = fm10k_sbus_read(sb, + FM10K_SW_SBUS_ADDR_EPL_SERDES(i), 0xff, &data); + if (error || data != 0x01) { + FM10K_SW_TRACE("sbus %s: skipping " + "serdes %u (error=%d, data=0x%08x)", sb->name, i, + error, data); + continue; + } + + error = fm10k_epl_serdes_spico_do_crc(sw, i); + if (error) + goto done; + + error = fm10k_epl_serdes_get_version_build_id(sw, i, + &version_build_id); + if (error) + goto done; + + if (version_build_id != expected_version_build_id) { + FM10K_SW_INFO("sbus %s: SERDES SPICO code " + "version compare failed (expected 0x%08x, got " + "0x%08x)", sb->name, expected_version_build_id, + version_build_id); + error = -1; + goto done; + } + } + FM10K_SW_TRACE("sbus %s: serdes %u through %u are OK", + sb->name, first, last); + +done: + return (error); +} + +static int +fm10k_epl_serdes_spico_do_crc(struct fm10k_switch *sw, unsigned int serdes) +{ + struct fm10k_sbus *sb = sw->epl_sbus; + int error; + uint32_t crc; + + FM10K_SW_TRACE("sbus %s: serdes %u: performing SPICO " + "CRC check", sb->name, serdes); + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x3c, 0, &crc); + if (error) + goto done; + + if (crc != 0) { + FM10K_SW_INFO("sbus %s: serdes %u: SPICO CRC check " + "failed (CRC interrupt returned 0x%08x)", + sb->name, serdes, crc); + error = -1; + goto done; + } + +done: + return (error); +} + +static int +fm10k_epl_serdes_spico_reset(struct fm10k_switch *sw, unsigned int serdes) +{ + struct fm10k_sbus *sb = sw->epl_sbus; + int error; + uint32_t data; + uint8_t addr = FM10K_SW_SBUS_ADDR_EPL_SERDES(serdes); + + FM10K_SW_TRACE("sbus %s: serdes %u: resetting SPICO", + sb->name, serdes); + + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + error = fm10k_sbus_write(sb, addr, 0, 0x00); + if (error) + goto done; + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + + data = (1 << 0) | (1 << 4); + error = fm10k_sbus_write(sb, addr, 0x07, data); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + + data = (1 << 18) | (1 << 19); + error = fm10k_sbus_write(sb, addr, 0x0b, data); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + + data = (1 << 4); + error = fm10k_sbus_write(sb, addr, 0x07, data); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + + data = (1 << 1); + error = fm10k_sbus_write(sb, addr, 0x07, data); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + + error = fm10k_sbus_write(sb, addr, 0x08, 0); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_get_version_build_id(struct fm10k_switch *sw, + unsigned int serdes, uint32_t *version_build_id) +{ + int error; + uint32_t data; + + FM10K_SW_TRACE("sbus %s: serdes %u: getting code " + "version", sw->epl_sbus->name, serdes); + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x00, 0, &data); + if (error) + goto done; + + *version_build_id = data << 16; + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x3f, 0, &data); + if (error) + goto done; + + *version_build_id |= data & 0xffff; +done: + return (error); +} + +static int +fm10k_sbm_spico_int(struct fm10k_sbus *sb, + uint8_t int_num, uint32_t param, uint32_t *result) +{ + uint64_t start_time_us, elapsed_time_ms; + uint32_t data; + int error; + + FM10K_SW_TRACE("sbus %s: SBM interrupt 0x%02x " + "(param=0x%08x)", sb->name, int_num, param); + + /* int write */ + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x02, + (param << 16) | int_num); + if (error) + goto done; + + error = fm10k_sbus_read(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x07, &data); + if (error) + goto done; + + data |= (1 << 0); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x07, data); + if (error) + goto done; + + data &= ~(1 << 0); + error = fm10k_sbus_write(sb, FM10K_SW_SBUS_ADDR_SPICO, 0x07, data); + if (error) + goto done; + + /* int read */ + start_time_us = fm10k_uptime_us(); + elapsed_time_ms = 0; + while (elapsed_time_ms < FM10K_SW_SBM_INTERRUPT_TIMEOUT_MS) { + elapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000; + error = fm10k_sbus_read(sb, + FM10K_SW_SBUS_ADDR_SPICO, 0x08, &data); + if (error) + goto done; + + if ((data & 0x8000) || ((data & 0x3ff) == 0)) { + if (elapsed_time_ms > 5) + fm10k_udelay(5); + } else { + FM10K_SW_TRACE("sbus %s: SBM " + "interrupt 0x%02x (param=0x%08x, result=0x%08x)", + sb->name, int_num, param, data); + *result = data; + goto done; + } + } + error = -1; + FM10K_SW_INFO("sbus %s: SBM interrupt timed out after %u " + "ms", sb->name, (uint32_t)elapsed_time_ms); + +done: + return (error); +} + +static int +fm10k_epl_serdes_spico_int(struct fm10k_switch *sw, + unsigned int serdes, uint16_t int_num, + uint32_t param, uint32_t *result) +{ + struct fm10k_sbus *sb = sw->epl_sbus; + uint64_t start_time_us, elapsed_time_ms; + unsigned int sbus_addr; + int error; + uint32_t data, intr; + + sbus_addr = FM10K_SW_SBUS_ADDR_EPL_SERDES(serdes); + + FM10K_SW_TRACE("sbus %s: serdes %u: (sbus addr 0x%02x) " + "interrupt 0x%04x (param=0x%08x)", sb->name, serdes, sbus_addr, + int_num, param); + + /* int write */ + start_time_us = fm10k_uptime_us(); + elapsed_time_ms = 0; + while (elapsed_time_ms < FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) { + elapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000; + error = fm10k_sbus_read(sb, sbus_addr, 0x04, &data); + if (error) + goto done; + + if (data & ((1 << 16) | (1 << 17))) { + if (elapsed_time_ms > 5) + fm10k_udelay(5); + } else { + break; + } + } + if (elapsed_time_ms >= FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) { + error = fm10k_sbus_read(sb, sbus_addr, 0x03, &intr); + FM10K_SW_INFO("sbus %s: serdes %u: interrupt timed out " + "after %u ms (intr=0x%04x param=0x%04x error=%u " + "reg[4]=0x%08x)", sb->name, serdes, + (uint32_t)elapsed_time_ms, intr >> 16, intr & 0xffff, error, + data); + error = -1; + goto done; + } else { + error = fm10k_sbus_write(sb, sbus_addr, 0x03, + ((uint32_t)int_num << 16) | param); + if (error) + goto done; + } + + /* int read */ + start_time_us = fm10k_uptime_us(); + elapsed_time_ms = 0; + while (elapsed_time_ms < FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) { + elapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000; + error = fm10k_sbus_read(sb, sbus_addr, 0x04, &data); + if (error) + goto done; + + if (data & ((1 << 16) | (1 << 17))) { + if (elapsed_time_ms > 5) + fm10k_udelay(5); + } else { + break; + } + } + if (elapsed_time_ms >= FM10K_SW_SERDES_INTERRUPT_TIMEOUT_MS) { + error = fm10k_sbus_read(sb, sbus_addr, 0x03, &intr); + FM10K_SW_INFO("sbus %s: serdes %u: interrupt timed out " + "(2) after %u ms (intr=0x%04x param=0x%04x error=%u " + "reg[4]=0x%08x)", sb->name, serdes, + (uint32_t)elapsed_time_ms, intr >> 16, intr & 0xffff, error, + data); + error = -1; + goto done; + } else { + FM10K_SW_TRACE("sbus %s: serdes %u: interrupt " + "0x%04x (param=0x%08x, result=0x%08x)", sb->name, serdes, + int_num, param, data); + if (result) + *result = data; + } + +done: + return (error); +} + + +int +fm10k_epl_serdes_start_bringup(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + unsigned int speed = lane->port->lane_speed; + unsigned int divider, width_mode; + int error = 0; + uint32_t data; + + /* + * Bit rate and width + */ + if (speed == 25) { + /* 25G */ + divider = FM10K_SW_SERDES_DIVIDER_ETHMODE_25G; + width_mode = FM10K_SW_SERDES_WIDTH_40; + } else { + /* 10G */ + divider = FM10K_SW_SERDES_DIVIDER_ETHMODE_10G; + width_mode = FM10K_SW_SERDES_WIDTH_20; + } + + /* + * state = CONFIGURED + */ + + FM10K_SW_TRACE("sbus %s: serdes %u: configuring", + sw->epl_sbus->name, serdes); + + error = fm10k_epl_serdes_spico_reset(sw, serdes); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_do_crc(sw, serdes); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + error = fm10k_epl_serdes_set_bit_rate(sw, serdes, divider); + if (error) + goto done; + + fm10k_epl_serdes_set_pcsl_width_mode(sw, serdes, + width_mode); + + /* + * Data select + */ + FM10K_SW_TRACE("sbus %s: serdes %u: setting TX data select", + sw->epl_sbus->name, serdes); + error = fm10k_epl_serdes_spico_int02_retry(sw, serdes, 0x1ff, + FM10K_SW_SERDES_INT02_TIMEOUT_MS); + if (error) + goto done; + + error = fm10k_epl_serdes_dma_reg_write(sw, serdes, 0x21, 0x0c00); + if (error) + goto done; + + /* + * Configure TX equalization + * + * Use defaults - copper and optical are the same. + * + * DEFAULTS| precursor | cursor | postcursor | + * --------+-----------+--------+------------+ + * copper | 0 | 0 | 15 | + * --------+-----------+--------+------------+ + * optical| 0 | 0 | 15 | + * --------+-----------+--------+------------+ + */ + FM10K_SW_TRACE("sbus %s: serdes %u: setting TX cursors", + sw->epl_sbus->name, serdes); + error = fm10k_epl_serdes_set_tx_eq(sw, serdes, + FM10K_SW_SERDES_EQ_SEL_ATTEN, 0); + if (error) + goto done; + error = fm10k_epl_serdes_set_tx_eq(sw, serdes, + FM10K_SW_SERDES_EQ_SEL_PRECUR, 0); + if (error) + goto done; + error = fm10k_epl_serdes_set_tx_eq(sw, serdes, + FM10K_SW_SERDES_EQ_SEL_POSTCUR, 15); + if (error) + goto done; + + /* + * Configure 'options', which means: + * - PLL calibration mode + * - Phase slip + * - RX termination + */ + FM10K_SW_TRACE("sbus %s: serdes %u: setting PLL calibration mode", + sw->epl_sbus->name, serdes); + /* enable PLL calibration */ + data = (1 << 0) | (1 << 1); + error = + fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x11, data); + if (error) + goto done; + /* There appears to be no action to take for phase slip */ + FM10K_SW_TRACE("sbus %s: serdes %u: configuring RX termination", + sw->epl_sbus->name, serdes); + /* RX termination appears to default to AVDD */ + data = (1 << 0); + error = + fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x2b, data); + if (error) + goto done; + + /* + * Set TX and RX lane polarity. + * Assuming no inversion required. + */ + FM10K_SW_TRACE("sbus %s: serdes %u: configuring TX/RX lane polarity", + sw->epl_sbus->name, serdes); + data = 0x0300; + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x13, data, NULL); + if (error) + goto done; + + /* + * Force local fault + */ + fm10k_epl_serdes_set_signal_detect(lane, + FM10K_SW_LANE_OVERRIDE_FORCE_BAD); + + /* + * Enable TX/RX + */ + FM10K_SW_TRACE("sbus %s: serdes %u: enabling TX/RX", + sw->epl_sbus->name, serdes); + fm10k_epl_serdes_set_signal_detect(lane, + FM10K_SW_LANE_OVERRIDE_FORCE_BAD); + error = + fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x01, 0x03); + if (error) + goto done; + + /* + * Clear and enable interrupts + */ + FM10K_SW_TRACE("sbus %s: serdes %u: configuring interrupts", + sw->epl_sbus->name, serdes); + error = fm10k_sbus_write(sw->epl_sbus, + FM10K_SW_SBUS_ADDR_EPL_SERDES(serdes), 0x08, 0); + if (error) + goto done; + +done: + return (error); +} + +int +fm10k_epl_serdes_continue_bringup(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + unsigned int speed = lane->port->lane_speed; + unsigned int width_mode; + int error = 0; + int near_loopback = sw->serdes_loopback; + + if (speed == 25) { + /* 25G */ + width_mode = FM10K_SW_SERDES_WIDTH_40; + } else { + /* 10G */ + width_mode = FM10K_SW_SERDES_WIDTH_20; + } + + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + error = fm10k_epl_serdes_set_pcsl_bit_slip(sw, serdes); + if (error) + goto done; + + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + error = fm10k_epl_serdes_set_width_mode(sw, serdes, width_mode); + if (error) + goto done; + + FM10K_SW_TRACE("sbus %s: serdes %u: enabling TX output", + sw->epl_sbus->name, serdes); + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + error = + fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x01, 0x07); + if (error) + goto done; + + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + error = fm10k_epl_serdes_init_signal_ok(sw, serdes, 0); + if (error) + goto done; + + if (near_loopback) { + /* enable near loopback */ + error = fm10k_epl_serdes_configure_near_loopback(lane); + if (error) + goto done; + } + +done: + return (error); +} + +int +fm10k_epl_serdes_disable(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + int error = 0; + + fm10k_epl_serdes_set_signal_detect(lane, + FM10K_SW_LANE_OVERRIDE_FORCE_BAD); + + /* XXX is this delay necessary? in some places the IES SDK does this */ + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + error = fm10k_epl_serdes_spico_reset(sw, serdes); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_set_bit_rate(struct fm10k_switch *sw, + unsigned int serdes, unsigned int divider) +{ + int error; + uint32_t data; + + FM10K_SW_TRACE("sbus %s: serdes %u: setting bit rate", + sw->epl_sbus->name, serdes); + + data = divider & 0x7ff; + data |= (1 << 12); + data |= (1 << 15); + + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x05, data); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_set_width_mode(struct fm10k_switch *sw, + unsigned int serdes, unsigned int width_mode) +{ + int error; + uint32_t data; + + FM10K_SW_TRACE("sbus %s: serdes %u: setting width mode to %u", + sw->epl_sbus->name, serdes, width_mode); + + data = FM10K_SW_SERDES_WIDTH_20 | (FM10K_SW_SERDES_WIDTH_20 << 4); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x14, data); + if (error) + goto done; + + data = width_mode | (width_mode << 4); + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x14, data); + if (error) + goto done; + +done: + fm10k_udelay(FM10K_SW_SERDES_RESET_DELAY_US); + return error; +} + +static int +fm10k_epl_serdes_set_tx_eq(struct fm10k_switch *sw, + unsigned int serdes, unsigned int which, unsigned int tx_eq) +{ + int error; + uint32_t data; + + FM10K_SW_TRACE("sbus %s: serdes %u: setting TX cursor %u to %u", + sw->epl_sbus->name, serdes, which, tx_eq); + + data = (tx_eq & 0xff) | (which << 14); + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x15, data); + if (error) + goto done; + +done: + return error; +} + +void +fm10k_epl_serdes_set_signal_detect(struct fm10k_ext_port_lane *lane, + unsigned int override) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int eplno = lane->port->eplno; + uint32_t data; + + FM10K_SW_TRACE("sbus %s: serdes %u: setting signal detect to %s", + sw->epl_sbus->name, lane->abs_laneno, + (override == 0) ? "NORMAL" : + (override == 1) ? "FORCE_GOOD" : + (override == 2) ? "FORCE_BAD" : ""); + + FM10K_SW_SWITCH_LOCK(sw); + data = fm10k_read_switch_reg(sw, + FM10K_SW_LANE_SIGNAL_DETECT_CFG(eplno, lane->rel_laneno)); + FM10K_SW_REPLACE_REG_FIELD(data, + LANE_SIGNAL_DETECT_CFG_SD_OVERRIDE, + override, data); + fm10k_write_switch_reg(sw, + FM10K_SW_LANE_SIGNAL_DETECT_CFG(eplno, lane->rel_laneno), data); + FM10K_SW_SWITCH_UNLOCK(sw); +} + +static void +fm10k_epl_serdes_set_pcsl_width_mode(struct fm10k_switch *sw, + unsigned int serdes, unsigned int width_mode) +{ + unsigned int eplno, lane; + uint32_t pcsl_cfg; + + FM10K_SW_TRACE("sbus %s: serdes %u: setting pcsl width mode", + sw->epl_sbus->name, serdes); + + fm10k_epl_serdes_eplno_lane(sw, serdes, &eplno, &lane); + + FM10K_SW_SWITCH_LOCK(sw); + pcsl_cfg = fm10k_read_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane)); + if (width_mode == FM10K_SW_SERDES_WIDTH_40) { + pcsl_cfg &= ~FM10K_SW_PCSL_CFG_RX_GB_NARROW; + pcsl_cfg &= ~FM10K_SW_PCSL_CFG_TX_GB_NARROW; + } else { + pcsl_cfg |= FM10K_SW_PCSL_CFG_RX_GB_NARROW; + pcsl_cfg |= FM10K_SW_PCSL_CFG_TX_GB_NARROW; + } + pcsl_cfg &= ~FM10K_SW_PCSL_CFG_RX_BIT_SLIP_ENABLE; + fm10k_write_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane), pcsl_cfg); + FM10K_SW_SWITCH_UNLOCK(sw); +} + +static int +fm10k_epl_serdes_set_pcsl_bit_slip(struct fm10k_switch *sw, + unsigned int serdes) +{ + unsigned int eplno, lane; + int error; + uint32_t int_return, pcsl_cfg; + + FM10K_SW_TRACE("sbus %s: serdes %u: setting pcsl bit slip", + sw->epl_sbus->name, serdes); + + fm10k_epl_serdes_eplno_lane(sw, serdes, &eplno, &lane); + error = + fm10k_epl_serdes_spico_int(sw, serdes, 0x0c, (1 << 7), &int_return); + if (error) + goto done; + + FM10K_SW_SWITCH_LOCK(sw); + pcsl_cfg = fm10k_read_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane)); + pcsl_cfg |= FM10K_SW_PCSL_CFG_RX_BIT_SLIP_ENABLE; + if (int_return & 0x1) + pcsl_cfg |= FM10K_SW_PCSL_CFG_RX_BIT_SLIP_INITIAL; + fm10k_write_switch_reg(sw, FM10K_SW_PCSL_CFG(eplno, lane), pcsl_cfg); + FM10K_SW_SWITCH_UNLOCK(sw); + + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x0c, (1 << 8)); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_init_signal_ok(struct fm10k_switch *sw, + unsigned int serdes, unsigned int threshold) +{ + int error; + + FM10K_SW_TRACE("sbus %s: serdes %u: setting signal OK threshold to %u", + sw->epl_sbus->name, serdes, threshold); + + error = + fm10k_epl_serdes_spico_int(sw, serdes, 0x20, 0x20, NULL); + if (error) + goto done; + + error = fm10k_epl_serdes_dma_esb_read_modify_write(sw, serdes, 0x080, + (threshold & 0xf) << 2, 0x3c, NULL); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_spico_int02_retry(struct fm10k_switch *sw, + unsigned int serdes, uint32_t data, unsigned int timeout_ms) +{ + uint64_t start_time_us, elapsed_time_ms; + uint32_t result; + int error; + + start_time_us = fm10k_uptime_us(); + elapsed_time_ms = 0; + while (elapsed_time_ms < timeout_ms) { + elapsed_time_ms = (fm10k_uptime_us() - start_time_us) / 1000; + error = + fm10k_epl_serdes_spico_int(sw, serdes, 0x02, data, &result); + if (result == 0x02) { + error = 0; + break; + } + + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + } + + return (error); +} + +static int +fm10k_epl_serdes_dma_reg_write(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, uint32_t data) +{ + int error; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x18, + 0x8000 | (addr & 0xff), NULL); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x19, data, NULL); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_dma_esb_read(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, uint32_t *result) +{ + int error; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x18, + 0x4000 | (addr & 0x3fff), result); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x1a, 0x00, result); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_dma_esb_write(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, uint32_t data) +{ + int error; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x18, + 0x4000 | (addr & 0x3fff), NULL); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x19, data, NULL); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_dma_esb_read_modify_write(struct fm10k_switch *sw, + unsigned int serdes, unsigned int addr, + uint32_t data, uint32_t mask, uint32_t *result) +{ + int error; + uint32_t read_data; + + error = fm10k_epl_serdes_dma_esb_read(sw, serdes, addr, &read_data); + if (error) + goto done; + + error = fm10k_epl_serdes_dma_esb_write(sw, serdes, addr, + (data & mask) | (read_data & ~mask)); + if (error) + goto done; + if (result) + *result = (data & mask) | (read_data & ~mask); +done: + return (error); +} + +static int +fm10k_epl_serdes_spico_wr_only_int(struct fm10k_switch *sw, + unsigned int serdes, unsigned int int_num, uint32_t param) +{ + int error; + uint32_t result; + + error = fm10k_epl_serdes_spico_int(sw, serdes, int_num, param, &result); + if (error) + goto done; + if (result != int_num) { + error = -1; + goto done; + } +done: + return (error); +} + +static void +fm10k_epl_serdes_eplno_lane(struct fm10k_switch *sw, + unsigned int serdes, unsigned int *eplno, unsigned int *lane) +{ + if (sw) { + *eplno = serdes / FM10K_SW_EPL_LANES; + *lane = serdes % FM10K_SW_EPL_LANES; + } +} + +static int +fm10k_epl_serdes_configure_near_loopback(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + uint32_t data; + int error; + + FM10K_SW_TRACE("sbus %s: serdes %u: configuring near loopback", + sw->epl_sbus->name, serdes); + + /* XXX assuming no lane polarity has been set */ + + /* set near loopback mode */ + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + data = (1 << 8) | (1 << 0); + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x08, data); + if (error) + goto done; + + /* disable tx output, leave tx/ex enabled */ + fm10k_udelay(FM10K_SW_SERDES_CONFIG_DELAY_US); + error = + fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x01, 0x03); + if (error) + goto done; + + /* set signal detect override to normal */ + fm10k_epl_serdes_set_signal_detect(lane, FM10K_SW_LANE_OVERRIDE_NORMAL); + +done: + return (error); +} + +int +fm10k_epl_serdes_configure_for_dfe_tuning(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + int error; + + FM10K_SW_TRACE("sbus %s: serdes %u: configuring serdes for dfe tuning", + sw->epl_sbus->name, serdes); + + /* + * Configure the serdes to run DFE tuning + */ + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x26, + ((2 << 12) | (0 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_HF & 0xff)), + NULL); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x26, + ((2 << 12) | (1 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_LF & 0xff)), + NULL); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x26, + ((2 << 12) | (2 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_DC & 0xff)), + NULL); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x26, + ((2 << 12) | (3 << 8) | (FM10K_SW_SERDES_DFE_DEFAULT_BW & 0xff)), + NULL); + if (error) + goto done; + + /* allow early link up */ + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x26, 0x5b01, NULL); + if (error) + goto done; + +done: + return (error); +} + +int +fm10k_epl_serdes_start_dfe_ical(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + unsigned int speed = lane->port->lane_speed; + int error; + uint32_t param; + + /* + * Start DFE tuning initial calibration (ical) + */ + FM10K_SW_TRACE("sbus %s: serdes %u: starting dfe ical", + sw->epl_sbus->name, serdes); + + if (speed == 25) + param = FM10K_SW_LINK_OPT_PARAM_A25G; + else + param = FM10K_SW_LINK_OPT_PARAM_A10G; + + if ((sw->epl_serdes_code_version_build_id >> 16) > 0x1055) + error = fm10k_epl_serdes_config_dfe_param(sw, serdes, param); + + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x0a, 0x01); + if (error) + goto done; + +done: + return (error); +} + +int +fm10k_epl_serdes_dfe_ical_status(struct fm10k_ext_port_lane *lane, + uint32_t *status) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + int error; + uint32_t dfe_status, converged; + + error = fm10k_epl_serdes_get_dfe_status(sw, serdes, &dfe_status); + if (error) + goto done; + + if ((dfe_status & 0x11) == 0x11) { + *status = FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS; + } else { + error = fm10k_epl_serdes_get_ical_result(sw, + serdes, &converged); + if (error) + goto done; + if (converged) + *status = FM10K_SW_SERDES_DFE_ICAL_CONVERGED; + else + *status = FM10K_SW_SERDES_DFE_ICAL_FAILED; + } + +done: + return (error); +} + +int +fm10k_epl_serdes_start_dfe_pcal(struct fm10k_ext_port_lane *lane) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + unsigned int speed = lane->port->lane_speed; + int error; + uint32_t param; + + /* + * Start DFE tuning periodic calibration (pcal), just one + */ + FM10K_SW_TRACE("sbus %s: serdes %u: starting dfe pcal", + sw->epl_sbus->name, serdes); + if (speed == 25) + param = FM10K_SW_LINK_OPT_PARAM_B25G; + else + param = FM10K_SW_LINK_OPT_PARAM_B10G; + + if ((sw->epl_serdes_code_version_build_id >> 16) > 0x1055) + error = fm10k_epl_serdes_config_dfe_param(sw, serdes, param); + + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x0a, 0x02); + if (error) + goto done; + +done: + return (error); +} + +int +fm10k_epl_serdes_dfe_pcal_status(struct fm10k_ext_port_lane *lane, + uint32_t *status) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + int error; + uint32_t dfe_status; + + error = fm10k_epl_serdes_get_dfe_status(sw, serdes, &dfe_status); + if (error) + goto done; + if (dfe_status & 0x02) + *status = FM10K_SW_SERDES_DFE_PCAL_COMPLETE; + else + *status = FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS; + +done: + return (error); +} + +int +fm10k_epl_serdes_stop_dfe_tuning(struct fm10k_ext_port_lane *lane, + unsigned int force_reset) +{ + struct fm10k_switch *sw = lane->port->ports->sw; + unsigned int serdes = lane->abs_laneno; + int error; + unsigned int ical_stopped, pcal_stopped; + unsigned int i; + uint32_t dfe_status, status; + + error = fm10k_epl_serdes_get_dfe_status(sw, serdes, &dfe_status); + if (error) + goto done; + + ical_stopped = 0; + pcal_stopped = 0; + + if (!force_reset) { + if (dfe_status & 0x3) { + /* stop all DFE tuning */ + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, + 0x0a, 0); + if (error) + goto done; + + for (i = 0; + i < FM10K_SW_SERDES_ICAL_STOP_MAX_CYCLES; + i++) { + error = fm10k_epl_serdes_dfe_ical_status(lane, + &status); + if (error) + goto done; + if (status != + FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS) { + ical_stopped = 1; + break; + } + fm10k_udelay + (FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US); + } + + if (ical_stopped) + for (i = 0; + i < FM10K_SW_SERDES_PCAL_STOP_MAX_CYCLES; + i++) { + error = + fm10k_epl_serdes_dfe_pcal_status + (lane, &status); + if (error) + goto done; + if (status != + FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS) { + pcal_stopped = 0; + break; + } + fm10k_udelay + (FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US); + } + } + + if (ical_stopped && pcal_stopped && (dfe_status & 0x40)) { + error = fm10k_epl_serdes_start_dfe_pcal(lane); + if (error) + goto done; + pcal_stopped = 0; + for (i = 0; + i < FM10K_SW_SERDES_PCAL_STOP_MAX_CYCLES; i++) { + error = fm10k_epl_serdes_dfe_pcal_status(lane, + &status); + if (error) + goto done; + if (status != + FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS) { + pcal_stopped = 1; + break; + } + fm10k_udelay + (FM10K_SW_SERDES_DFE_STOP_CYCLE_DELAY_US); + } + } + } + + if (!ical_stopped || !pcal_stopped) { + error = -1; + goto done; + } + +done: + return (error); +} + +static int +fm10k_epl_serdes_config_dfe_param(struct fm10k_switch *sw, + unsigned int serdes, uint32_t param) +{ + int error; + + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x18, 0x07); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x19, + param & 0xffff); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_wr_only_int(sw, serdes, 0x19, + param >> 16); + if (error) + goto done; + +done: + return (error); +} + +static int +fm10k_epl_serdes_get_dfe_status(struct fm10k_switch *sw, + unsigned int serdes, uint32_t *status) +{ + int error; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x126, (0x0b << 8), + status); + if (error) + goto done; + + FM10K_SW_TRACE("sbus %s: serdes %u: dfe status: " + "coarse_active=%u fine_active=%u adaptive=%u", + sw->epl_sbus->name, serdes, *status & (1 << 0), + *status & (1 << 1), *status & (1 << 6)); + +done: + return (error); +} + +static int +fm10k_epl_serdes_get_ical_result(struct fm10k_switch *sw, + unsigned int serdes, uint32_t *converged) +{ + uint32_t val1; + uint32_t val2; + uint32_t diff; + int error; + + *converged = 0; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x126, + (4 << 12), &val1); + if (error) + goto done; + + error = fm10k_epl_serdes_spico_int(sw, serdes, 0x126, + (4 << 12) | (1 << 8), &val2); + if (error) + goto done; + + /* sign extension */ + if (val1 & 0x8000) + val1 |= 0xffff0000; + if (val2 & 0x8000) + val2 |= 0xffff0000; + diff = abs(val2 - val1); + + if (diff >= FM10K_SW_SERDES_DFE_DATA_LEVEL0_THRESHOLD) + *converged = 1; + +done: + return (error); +} diff --git a/drivers/net/fm10k/switch/fm10k_serdes.h b/drivers/net/fm10k/switch/fm10k_serdes.h new file mode 100644 index 0000000..d7c07b1 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_serdes.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_SW_SERDES_H_ +#define _FM10K_SW_SERDES_H_ + + +#define FM10K_SW_SERDES_DFE_ICAL_IN_PROGRESS 0 +#define FM10K_SW_SERDES_DFE_ICAL_CONVERGED 1 +#define FM10K_SW_SERDES_DFE_ICAL_FAILED 2 +#define FM10K_SW_SERDES_DFE_PCAL_IN_PROGRESS 0 +#define FM10K_SW_SERDES_DFE_PCAL_COMPLETE 1 + + +int fm10k_epl_serdes_reset_and_load_all(struct fm10k_switch *sw); +int fm10k_epl_serdes_start_bringup(struct fm10k_ext_port_lane *lane); +int fm10k_epl_serdes_continue_bringup(struct fm10k_ext_port_lane *lane); +int fm10k_epl_serdes_disable(struct fm10k_ext_port_lane *lane); +int fm10k_epl_serdes_configure_for_dfe_tuning(struct fm10k_ext_port_lane *lane); +int fm10k_epl_serdes_start_dfe_ical(struct fm10k_ext_port_lane *lane); +int fm10k_epl_serdes_dfe_ical_status + (struct fm10k_ext_port_lane *lane, uint32_t *status); +int fm10k_epl_serdes_start_dfe_pcal(struct fm10k_ext_port_lane *lane); +int fm10k_epl_serdes_dfe_pcal_status + (struct fm10k_ext_port_lane *lane, uint32_t *status); +int fm10k_epl_serdes_stop_dfe_tuning + (struct fm10k_ext_port_lane *lane, unsigned int force_reset); +void fm10k_epl_serdes_set_signal_detect + (struct fm10k_ext_port_lane *lane, unsigned int override); + +#endif /* _FM10K_SW_SERDES_H_ */ diff --git a/drivers/net/fm10k/switch/fm10k_sm.c b/drivers/net/fm10k/switch/fm10k_sm.c new file mode 100644 index 0000000..74fb023 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_sm.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#include +#include +#include + +#include "../base/fm10k_osdep.h" +#include "fm10k_debug.h" +#include "fm10k_sm.h" + +static void *fm10k_sm_handle_event(void *ptr); +static void *fm10k_sm_handle_timer(void *ptr); +static void fm10k_sm_event_heap_init(struct fm10k_sm_event_heap *heap); +static uint16_t fm10k_sm_event_heap_pop(struct fm10k_sm_event_heap *heap); +static void fm10k_sm_event_heap_push + (struct fm10k_sm_event_heap *heap, uint16_t id); + + +struct fm10k_sm * +fm10k_sm_attach(uint16_t num_events, + uint16_t num_timers, fm10k_sm_process_event_t event_handler, + fm10k_sm_process_timer_t timer_handler, void *ctx) +{ + struct fm10k_sm *sm; + struct fm10k_sm_timer *timer; + unsigned int i; + + sm = (struct fm10k_sm *)rte_zmalloc("fm10k_sm", + sizeof(struct fm10k_sm), 0); + if (sm == NULL) + goto fail; + + sm->num_events = num_events; + fm10k_sm_event_heap_init(&sm->events); + pthread_create(&sm->event_task, NULL, fm10k_sm_handle_event, sm); + sm->num_timers = num_timers; + if (sm->num_timers > 0) { + sm->timers = (struct fm10k_sm_timer *)rte_zmalloc("fm10k_sm_timers", + sizeof(struct fm10k_sm_timer) * sm->num_timers, 0); + if (sm->timers == NULL) + goto fail; + } + + sm->event_handler = event_handler; + sm->timer_handler = timer_handler; + sm->ctx = ctx; + + for (i = 0; i < sm->num_timers; i++) { + timer = &sm->timers[i]; + sem_init(&timer->tq, 0, 0); + timer->sm = sm; + pthread_create(&timer->t, NULL, fm10k_sm_handle_timer, timer); + timer->timer_id = i; + } + + return sm; + +fail: + if (sm) + fm10k_sm_detach(sm); + + return NULL; +} + +void +fm10k_sm_detach(struct fm10k_sm *sm) +{ + rte_free(sm); +} + +void +fm10k_sm_send_event(struct fm10k_sm *sm, uint16_t event_id) +{ + fm10k_sm_event_heap_push(&sm->events, event_id); +} + +void +fm10k_sm_timer_start(struct fm10k_sm *sm, uint16_t timer_id, + unsigned int timeout_ms) +{ + struct fm10k_sm_timer *timer = &sm->timers[timer_id]; + + gettimeofday(&timer->start, 0); + timer->timeout_ms = timeout_ms; + timer->running = 1; + sem_post(&timer->tq); +} + +/* + * It is possible that an expiration events from this timer will + * occur after this is called. + */ +void +fm10k_sm_timer_cancel(struct fm10k_sm *sm, uint16_t timer_id) +{ + struct fm10k_sm_timer *timer = &sm->timers[timer_id]; + timer->running = 0; +} + +static void * +fm10k_sm_handle_event(void *ctx) +{ + struct fm10k_sm *sm = ctx; + uint16_t event_id; + + while (1) { + event_id = fm10k_sm_event_heap_pop(&sm->events); + sm->event_handler(sm, event_id); + } + return NULL; +} + +static void * +fm10k_sm_handle_timer(void *ctx) +{ + struct fm10k_sm_timer *timer = ctx; + struct fm10k_sm *sm = timer->sm; + struct timeval now; + struct timeval sleep; + uint64_t cost, timeout; + + while (1) { + sem_wait(&timer->tq); + if (timer->running) { + gettimeofday(&now, 0); + cost = (now.tv_sec - timer->start.tv_sec) * 1000000; + cost += (now.tv_usec - timer->start.tv_usec); + if (cost < timer->timeout_ms * 1000) { + timeout = timer->timeout_ms * 1000; + timeout -= cost; + sleep.tv_sec = timeout / 1000000; + sleep.tv_usec = timeout % 1000000; + select(0, NULL, NULL, NULL, &sleep); + } + if (timer->running) + sm->timer_handler(sm, timer->timer_id); + } + } + + return NULL; +} + + +static void +fm10k_sm_event_heap_init(struct fm10k_sm_event_heap *heap) +{ + heap->count = 0; + pthread_mutex_init(&heap->lock, NULL); + sem_init(&heap->s, 0, 0); +} + +static uint16_t +fm10k_sm_event_heap_pop(struct fm10k_sm_event_heap *heap) +{ + int i; + uint16_t id; + + sem_wait(&heap->s); + pthread_mutex_lock(&heap->lock); + id = heap->heap[0]; + for (i = 1; i < heap->count; i++) + heap->heap[i - 1] = heap->heap[i]; + heap->count--; + pthread_mutex_unlock(&heap->lock); + return id; +} + +static void +fm10k_sm_event_heap_push(struct fm10k_sm_event_heap *heap, uint16_t id) +{ + pthread_mutex_lock(&heap->lock); + if (heap->count >= FM10K_SM_ID_HEAP_MAX) { + pthread_mutex_unlock(&heap->lock); + return; + } + heap->heap[heap->count] = id; + heap->count++; + pthread_mutex_unlock(&heap->lock); + sem_post(&heap->s); +} diff --git a/drivers/net/fm10k/switch/fm10k_sm.h b/drivers/net/fm10k/switch/fm10k_sm.h new file mode 100644 index 0000000..1b6e3a9 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_sm.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_SW_SM_H_ +#define _FM10K_SW_SM_H_ + +#include + +#include +#include +#include +#include + +/* + * This framework provides state machine implementation support for use in + * the rest of the driver. + * + * The model is that for a given state machine, there are N>0 events + * identified by the integers [0..N-1] and there are M>=0 timers identified + * by the integers [0..M-1]. + * + * The timers are one-shot timers. + * + * Since all state machine processing occurs in the context of the + * task queue, if that task queue was created with only a single thread, then + * no locking is required in the provided event and timer handlers to + * prevent overlapping execution. + * + */ + +struct fm10k_sm; + +struct fm10k_sm_timer { + struct fm10k_sm *sm; + pthread_t t; + sem_t tq; + struct timeval start; + uint16_t timeout_ms; + uint16_t timer_id; + uint8_t running; +}; + +typedef void (*fm10k_sm_process_event_t)(struct fm10k_sm *sm, uint16_t event); +typedef void (*fm10k_sm_process_timer_t)(struct fm10k_sm *sm, uint16_t timer); + +#define FM10K_SM_ID_HEAP_MAX 128 +struct fm10k_sm_event_heap { + pthread_mutex_t lock; + sem_t s; + uint16_t count; + uint16_t heap[FM10K_SM_ID_HEAP_MAX]; +}; + +struct fm10k_sm { + pthread_t event_task; + struct fm10k_sm_timer *timers; + struct fm10k_sm_event_heap events; + fm10k_sm_process_event_t event_handler; + fm10k_sm_process_timer_t timer_handler; + void *ctx; + unsigned int state; + uint16_t num_events; + uint16_t num_timers; + uint8_t portno; + uint8_t laneno; +}; + +struct fm10k_sm *fm10k_sm_attach(uint16_t num_events, + uint16_t num_timers, fm10k_sm_process_event_t event_handler, + fm10k_sm_process_timer_t timer_handler, void *ctx); +void fm10k_sm_detach(struct fm10k_sm *sm); +void fm10k_sm_send_event(struct fm10k_sm *sm, uint16_t event_id); +void fm10k_sm_timer_start(struct fm10k_sm *sm, + uint16_t timer_id, unsigned int timeout_ms); +void fm10k_sm_timer_cancel(struct fm10k_sm *sm, uint16_t timer_id); + +#endif /* _FM10K_SW_SM_H_ */ diff --git a/drivers/net/fm10k/switch/fm10k_spico_code.c b/drivers/net/fm10k/switch/fm10k_spico_code.c new file mode 100644 index 0000000..cfab632 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_spico_code.c @@ -0,0 +1,2966 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#include "fm10k_spico_code.h" + + +/* Production versions */ + + +/* SBus master code (production version) + * source file: release_2015_01_14/sbus_master.0x1013_0001.rom + */ + +const uint32_t fm10000_sbus_master_code_version_build_id_prd = 0x10130001; +const uint32_t fm10000_sbus_master_code_size_prd = 3338; + +const uint16_t fm10000_sbus_master_code_prd[] = { + 0x132, 0x002, 0x006, 0x000, 0x390, 0x002, 0x080, 0x247, + 0x071, 0x247, 0x01f, 0x247, 0x020, 0x247, 0x02e, 0x247, + 0x02f, 0x247, 0x03f, 0x247, 0x040, 0x247, 0x042, 0x247, + 0x043, 0x247, 0x03d, 0x0c0, 0x02d, 0x247, 0x031, 0x247, + 0x032, 0x081, 0x18b, 0x247, 0x039, 0x248, 0x03a, 0x181, + 0x247, 0x034, 0x248, 0x036, 0x209, 0x247, 0x033, 0x248, + 0x035, 0x305, 0x034, 0x247, 0x037, 0x248, 0x038, 0x190, + 0x247, 0x03b, 0x248, 0x03c, 0x3d4, 0x1ff, 0x00c, 0x3d5, + 0x100, 0x00c, 0x3d4, 0x2ff, 0x00c, 0x3c7, 0x0fe, 0x018, + 0x0c2, 0x019, 0x044, 0x233, 0x000, 0x152, 0x01b, 0x347, + 0x01b, 0x030, 0x085, 0x187, 0x247, 0x03e, 0x3c7, 0x100, + 0x041, 0x080, 0x247, 0x065, 0x3c4, 0x3fc, 0x010, 0x3d4, + 0x22f, 0x00e, 0x347, 0x033, 0x008, 0x247, 0x008, 0x081, + 0x189, 0x227, 0x2c7, 0x044, 0x220, 0x2c7, 0x045, 0x220, + 0x2c7, 0x046, 0x220, 0x2c7, 0x047, 0x220, 0x2c7, 0x048, + 0x220, 0x2c7, 0x049, 0x220, 0x2c7, 0x04a, 0x220, 0x2c7, + 0x04b, 0x3a7, 0x05b, 0x1a7, 0x3a5, 0x08d, 0x2c7, 0x04c, + 0x0c0, 0x04d, 0x044, 0x07d, 0x001, 0x0df, 0x02c, 0x000, + 0x009, 0x322, 0x02c, 0x009, 0x005, 0x347, 0x02d, 0x02c, + 0x3d4, 0x3df, 0x00e, 0x307, 0x02c, 0x384, 0x01f, 0x229, + 0x220, 0x3b0, 0x0aa, 0x287, 0x199, 0x390, 0x000, 0x041, + 0x040, 0x045, 0x020, 0x12c, 0x000, 0x020, 0x163, 0x000, + 0x020, 0x175, 0x000, 0x020, 0x27e, 0x000, 0x020, 0x362, + 0x000, 0x020, 0x10a, 0x000, 0x020, 0x10a, 0x000, 0x020, + 0x1de, 0x000, 0x020, 0x330, 0x001, 0x020, 0x270, 0x001, + 0x020, 0x2af, 0x001, 0x020, 0x2a1, 0x001, 0x020, 0x338, + 0x001, 0x020, 0x285, 0x001, 0x020, 0x2b9, 0x001, 0x020, + 0x2a8, 0x001, 0x020, 0x001, 0x002, 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0x027, + 0x019, 0x347, 0x028, 0x01b, 0x347, 0x029, 0x01c, 0x044, + 0x222, 0x000, 0x0a1, 0x000, 0x31e, 0x347, 0x026, 0x018, + 0x347, 0x027, 0x019, 0x044, 0x233, 0x000, 0x347, 0x01b, + 0x028, 0x347, 0x01c, 0x029, 0x0a2, 0x000, 0x30c, 0x044, + 0x1b9, 0x000, 0x362, 0x01b, 0x000, 0x001, 0x016, 0x362, + 0x01b, 0x001, 0x001, 0x013, 0x362, 0x01b, 0x002, 0x001, + 0x00d, 0x362, 0x01b, 0x003, 0x001, 0x013, 0x362, 0x01b, + 0x004, 0x001, 0x013, 0x04e, 0x045, 0x364, 0x03d, 0x002, + 0x001, 0x005, 0x044, 0x01a, 0x001, 0x000, 0x3f7, 0x348, + 0x01b, 0x01a, 0x000, 0x3f2, 0x348, 0x01b, 0x01a, 0x000, + 0x3ed, 0x101, 0x247, 0x018, 0x3d7, 0x0ff, 0x019, 0x000, + 0x074, 0x3c7, 0x100, 0x014, 0x364, 0x004, 0x100, 0x009, + 0x00f, 0x044, 0x08d, 0x001, 0x2c7, 0x042, 0x044, 0x1de, + 0x001, 0x001, 0x005, 0x044, 0x239, 0x001, 0x055, 0x0c1, + 0x03d, 0x0bf, 0x000, 0x2b7, 0x000, 0x2bc, 0x3c7, 0x3ff, + 0x028, 0x087, 0x0b6, 0x0c1, 0x04e, 0x044, 0x37c, 0x000, + 0x347, 0x067, 0x029, 0x2c7, 0x02a, 0x322, 0x04e, 0x009, + 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0x39c, 0x347, 0x011, 0x066, 0x3c4, 0x3fc, + 0x066, 0x364, 0x065, 0x040, 0x009, 0x0a3, 0x044, 0x085, + 0x003, 0x001, 0x06f, 0x044, 0x06b, 0x003, 0x001, 0x005, + 0x055, 0x000, 0x384, 0x044, 0x074, 0x003, 0x3c4, 0x37f, + 0x065, 0x1b5, 0x3a4, 0x038, 0x3c4, 0x3c7, 0x065, 0x2c5, + 0x065, 0x1b2, 0x2e2, 0x007, 0x001, 0x047, 0x2e2, 0x006, + 0x001, 0x043, 0x2e2, 0x002, 0x001, 0x047, 0x2e2, 0x001, + 0x001, 0x031, 0x3d7, 0x07f, 0x064, 0x0a6, 0x044, 0x0bf, + 0x003, 0x000, 0x35c, 0x364, 0x010, 0x002, 0x009, 0x005, + 0x364, 0x011, 0x001, 0x045, 0x3d5, 0x040, 0x00e, 0x3c5, + 0x001, 0x010, 0x3c4, 0x3bf, 0x065, 0x327, 0x066, 0x00b, + 0x005, 0x3c5, 0x040, 0x065, 0x045, 0x327, 0x004, 0x307, + 0x066, 0x198, 0x384, 0x038, 0x1b8, 0x3a4, 0x038, 0x222, + 0x045, 0x3b7, 0x010, 0x1a7, 0x3a5, 0x013, 0x2c7, 0x064, + 0x0a7, 0x000, 0x3cd, 0x347, 0x066, 0x064, 0x044, 0x0cd, + 0x003, 0x000, 0x324, 0x055, 0x0c4, 0x02c, 0x000, 0x31f, + 0x044, 0x074, 0x003, 0x3c5, 0x080, 0x065, 0x3c4, 0x3f8, + 0x065, 0x3a4, 0x1fc, 0x081, 0x245, 0x065, 0x1b1, 0x390, + 0x066, 0x04d, 0x3c5, 0x100, 0x065, 0x000, 0x308, 0x3c4, + 0x07f, 0x064, 0x1c1, 0x064, 0x307, 0x066, 0x198, 0x384, + 0x038, 0x285, 0x188, 0x245, 0x064, 0x3c4, 0x003, 0x010, + 0x345, 0x064, 0x010, 0x3c5, 0x002, 0x010, 0x045, 0x044, + 0x085, 0x003, 0x009, 0x009, 0x307, 0x065, 0x364, 0x065, + 0x080, 0x009, 0x00c, 0x044, 0x06b, 0x003, 0x009, 0x35a, + 0x044, 0x074, 0x003, 0x000, 0x3b0, 0x044, 0x074, 0x003, + 0x384, 0x007, 0x262, 0x007, 0x001, 0x2d1, 0x141, 0x065, + 0x101, 0x324, 0x035, 0x000, 0x3bb, 0x3d5, 0x010, 0x00e, + 0x055, 0x0d3, 0x02c, 0x000, 0x2c2, 0x04e, 0x062, 0x0b1, + 0x0e7, 0x079 + +}; /* end fm10000_sbus_master_code_prd */ + +/* Spico SerDes code (production version 2) + * source file: serdes.0x2055/serdes.0x2055_0045.rom + * KR support + */ +const uint32_t fm10000_serdes_spico_code_version_build_id_prd2 = 0x20550045; +const uint32_t fm10000_serdes_spico_code_size_prd2 = 12167; + +const uint16_t fm10000_serdes_spico_code_prd2[] = { + 0x035, 0x006, 0x00a, 0x000, 0x1a7, 0x006, 0x020, 0x055, + 0x000, 0x045, 0x3c7, 0x03f, 0x000, 0x0c0, 0x200, 0x307, + 0x200, 0x304, 0x02b, 0x009, 0x00b, 0x0a0, 0x397, 0x3bb, + 0x04d, 0x111, 0x272, 0x1ff, 0x009, 0x3fc, 0x3c8, 0x000, + 0x21e, 0x3ce, 0x3ff, 0x21f, 0x348, 0x21f, 0x21d, 0x34e, + 0x21d, 0x221, 0x34e, 0x221, 0x21c, 0x34e, 0x21c, 0x220, + 0x3c7, 0x3fd, 0x23d, 0x3c7, 0x020, 0x23e, 0x3c7, 0x077, + 0x22d, 0x0c0, 0x202, 0x044, 0x36d, 0x003, 0x044, 0x360, + 0x002, 0x3d7, 0x303, 0x030, 0x347, 0x032, 0x236, 0x3b7, + 0x213, 0x090, 0x044, 0x1a9, 0x000, 0x3b7, 0x204, 0x387, + 0x07c, 0x044, 0x1a9, 0x000, 0x0a4, 0x397, 0x27c, 0x044, + 0x1a9, 0x000, 0x3d5, 0x230, 0x232, 0x345, 0x21d, 0x232, + 0x3b7, 0x221, 0x081, 0x18b, 0x044, 0x1b7, 0x000, 0x3b7, + 0x080, 0x044, 0x192, 0x000, 0x385, 0x00c, 0x384, 0x3cf, + 0x044, 0x1bd, 0x000, 0x3c5, 0x040, 0x021, 0x3b7, 0x020, + 0x387, 0x021, 0x189, 0x044, 0x1a9, 0x000, 0x0c0, 0x008, + 0x0c0, 0x005, 0x0c0, 0x00b, 0x0c0, 0x000, 0x3c5, 0x020, + 0x027, 0x055, 0x307, 0x221, 0x304, 0x233, 0x009, 0x012, + 0x374, 0x027, 0x200, 0x001, 0x00d, 0x044, 0x340, 0x001, + 0x264, 0x080, 0x009, 0x006, 0x3b8, 0x200, 0x2c4, 0x027, + 0x054, 0x364, 0x200, 0x004, 0x029, 0x3de, 0x003, 0x364, + 0x33b, 0x010, 0x029, 0x3de, 0x003, 0x054, 0x364, 0x200, + 0x040, 0x029, 0x034, 0x008, 0x364, 0x2cf, 0x040, 0x009, + 0x01c, 0x307, 0x026, 0x384, 0x003, 0x266, 0x003, 0x009, + 0x014, 0x362, 0x26b, 0x0e0, 0x009, 0x00f, 0x364, 0x234, + 0x002, 0x001, 0x00a, 0x3c5, 0x060, 0x2cf, 0x0c0, 0x26b, + 0x3c5, 0x040, 0x200, 0x054, 0x364, 0x200, 0x100, 0x029, + 0x22f, 0x003, 0x054, 0x044, 0x141, 0x001, 0x055, 0x364, + 0x23f, 0x003, 0x001, 0x012, 0x044, 0x34c, 0x001, 0x029, + 0x0af, 0x006, 0x044, 0x340, 0x001, 0x227, 0x326, 0x249, + 0x1ba, 0x029, 0x0af, 0x006, 0x3c4, 0x3df, 0x000, 0x364, + 0x33c, 0x020, 0x001, 0x017, 0x364, 0x059, 0x080, 0x001, + 0x012, 0x364, 0x24b, 0x080, 0x009, 0x00d, 0x364, 0x001, + 0x080, 0x009, 0x008, 0x3c5, 0x080, 0x24b, 0x044, 0x12d, + 0x005, 0x055, 0x364, 0x200, 0x080, 0x001, 0x00d, 0x3c4, + 0x3fd, 0x26f, 0x3c4, 0x3fe, 0x200, 0x366, 0x200, 0x080, + 0x001, 0x00f, 0x140, 0x200, 0x009, 0x365, 0x364, 0x23f, + 0x003, 0x009, 0x360, 0x04f, 0x04e, 0x000, 0x35c, 0x3c5, + 0x030, 0x000, 0x347, 0x244, 0x054, 0x374, 0x000, 0x2c0, + 0x009, 0x34c, 0x387, 0x0c1, 0x187, 0x245, 0x054, 0x04f, + 0x055, 0x141, 0x26c, 0x347, 0x245, 0x200, 0x347, 0x245, + 0x26d, 0x0c0, 0x245, 0x364, 0x026, 0x002, 0x001, 0x336, + 0x364, 0x020, 0x005, 0x009, 0x007, 0x0c2, 0x26f, 0x044, + 0x1b8, 0x001, 0x055, 0x364, 0x020, 0x005, 0x009, 0x326, + 0x362, 0x26b, 0x0e0, 0x009, 0x321, 0x364, 0x234, 0x002, + 0x001, 0x31c, 0x3c5, 0x060, 0x2cf, 0x3c5, 0x040, 0x200, + 0x000, 0x314, 0x044, 0x290, 0x001, 0x3c5, 0x080, 0x200, + 0x347, 0x2cf, 0x26b, 0x3c4, 0x0e0, 0x26b, 0x3c4, 0x3bf, + 0x2cf, 0x045, 0x387, 0x080, 0x020, 0x2f8, 0x001, 0x387, + 0x02f, 0x111, 0x009, 0x3ff, 0x045, 0x054, 0x111, 0x009, + 0x3fe, 0x045, 0x044, 0x1a0, 0x000, 0x307, 0x032, 0x054, + 0x045, 0x044, 0x1a0, 0x000, 0x307, 0x033, 0x054, 0x045, + 0x055, 0x2c7, 0x030, 0x364, 0x035, 0x001, 0x009, 0x3fd, + 0x045, 0x044, 0x1a0, 0x000, 0x305, 0x033, 0x000, 0x012, + 0x044, 0x1a0, 0x000, 0x306, 0x033, 0x000, 0x00b, 0x208, + 0x044, 0x1a0, 0x000, 0x304, 0x033, 0x055, 0x2c7, 0x030, + 0x247, 0x031, 0x345, 0x21d, 0x030, 0x140, 0x035, 0x009, + 0x3fe, 0x346, 0x21d, 0x030, 0x054, 0x045, 0x040, 0x140, + 0x036, 0x00b, 0x020, 0x044, 0x206, 0x000, 0x344, 0x21f, + 0x036, 0x3c4, 0x3ef, 0x036, 0x09f, 0x044, 0x189, 0x000, + 0x000, 0x010, 0x040, 0x140, 0x036, 0x003, 0x00c, 0x044, + 0x206, 0x000, 0x345, 0x21d, 0x036, 0x3c4, 0x3ef, 0x036, + 0x054, 0x327, 0x22b, 0x3a4, 0x003, 0x133, 0x009, 0x00e, + 0x0a1, 0x1aa, 0x2a8, 0x2c4, 0x021, 0x08f, 0x044, 0x189, + 0x000, 0x2a8, 0x2c5, 0x021, 0x042, 0x045, 0x055, 0x088, + 0x3c5, 0x010, 0x036, 0x000, 0x37e, 0x3c4, 0x3fe, 0x026, + 0x327, 0x22c, 0x3a4, 0x007, 0x2e6, 0x001, 0x001, 0x01b, + 0x044, 0x1e2, 0x000, 0x364, 0x234, 0x001, 0x009, 0x013, + 0x364, 0x33b, 0x007, 0x001, 0x00d, 0x044, 0x3b6, 0x003, + 0x364, 0x33c, 0x020, 0x009, 0x005, 0x044, 0x066, 0x004, + 0x054, 0x045, 0x364, 0x233, 0x002, 0x009, 0x00d, 0x347, + 0x271, 0x270, 0x044, 0x2f6, 0x002, 0x009, 0x005, 0x044, + 0x02b, 0x008, 0x374, 0x232, 0x200, 0x001, 0x0a5, 0x3d7, + 0x200, 0x27b, 0x044, 0x29c, 0x001, 0x044, 0x2f6, 0x002, + 0x009, 0x005, 0x044, 0x028, 0x008, 0x3b7, 0x221, 0x364, + 0x22b, 0x003, 0x009, 0x007, 0x083, 0x18b, 0x044, 0x1a9, + 0x000, 0x398, 0x200, 0x244, 0x232, 0x3b7, 0x221, 0x091, + 0x189, 0x385, 0x128, 0x044, 0x1a9, 0x000, 0x083, 0x044, + 0x1b7, 0x000, 0x3b7, 0x220, 0x044, 0x192, 0x000, 0x197, + 0x264, 0x007, 0x009, 0x005, 0x091, 0x000, 0x003, 0x081, + 0x3b7, 0x221, 0x189, 0x044, 0x1b7, 0x000, 0x364, 0x246, + 0x010, 0x009, 0x002, 0x3b7, 0x221, 0x081, 0x18d, 0x044, + 0x1a9, 0x000, 0x081, 0x189, 0x044, 0x1a9, 0x000, 0x387, + 0x2d7, 0x044, 0x1b8, 0x000, 0x364, 0x22b, 0x003, 0x009, + 0x009, 0x3b7, 0x221, 0x081, 0x18b, 0x044, 0x1b7, 0x000, + 0x364, 0x02b, 0x020, 0x009, 0x020, 0x0a3, 0x364, 0x22b, + 0x003, 0x001, 0x006, 0x044, 0x025, 0x008, 0x0a0, 0x307, + 0x251, 0x197, 0x384, 0x00f, 0x220, 0x001, 0x005, 0x044, + 0x182, 0x000, 0x327, 0x251, 0x3a4, 0x01f, 0x001, 0x005, + 0x044, 0x0d9, 0x001, 0x044, 0x1ce, 0x000, 0x364, 0x232, + 0x100, 0x001, 0x005, 0x044, 0x0a9, 0x001, 0x3c4, 0x3f0, + 0x22d, 0x3c5, 0x001, 0x026, 0x364, 0x026, 0x002, 0x001, + 0x1c5, 0x044, 0x283, 0x001, 0x3b7, 0x300, 0x387, 0x020, + 0x000, 0x2c1, 0x307, 0x036, 0x00b, 0x3ea, 0x044, 0x1ce, + 0x000, 0x000, 0x3e5, 0x387, 0x3ff, 0x327, 0x22c, 0x3a4, + 0x007, 0x131, 0x001, 0x01a, 0x3d5, 0x200, 0x232, 0x000, + 0x006, 0x080, 0x131, 0x001, 0x011, 0x3b7, 0x205, 0x044, + 0x1bd, 0x000, 0x3b7, 0x222, 0x044, 0x1bd, 0x000, 0x3b7, + 0x251, 0x044, 0x1bd, 0x000, 0x3b7, 0x214, 0x100, 0x009, + 0x00a, 0x044, 0x1bd, 0x000, 0x3c4, 0x37b, 0x021, 0x000, + 0x29e, 0x3c5, 0x084, 0x021, 0x000, 0x299, 0x364, 0x233, + 0x002, 0x009, 0x00d, 0x347, 0x272, 0x270, 0x044, 0x2f6, + 0x002, 0x009, 0x005, 0x044, 0x02e, 0x008, 0x307, 0x22d, + 0x384, 0x070, 0x386, 0x010, 0x001, 0x04a, 0x364, 0x02b, + 0x020, 0x009, 0x045, 0x3b7, 0x071, 0x387, 0x128, 0x044, + 0x1a9, 0x000, 0x387, 0x368, 0x044, 0x1b8, 0x000, 0x387, + 0x2d7, 0x044, 0x1b8, 0x000, 0x0a1, 0x307, 0x22b, 0x384, + 0x030, 0x001, 0x003, 0x0ac, 0x307, 0x256, 0x384, 0x01f, + 0x220, 0x001, 0x005, 0x044, 0x0de, 0x001, 0x080, 0x327, + 0x22b, 0x3a4, 0x030, 0x3a2, 0x030, 0x009, 0x00e, 0x0a1, + 0x1ab, 0x2a8, 0x2c4, 0x024, 0x08f, 0x044, 0x189, 0x000, + 0x2a8, 0x2c5, 0x024, 0x327, 0x256, 0x1b7, 0x3a4, 0x07f, + 0x220, 0x001, 0x005, 0x044, 0x0e2, 0x001, 0x044, 0x2f6, + 0x002, 0x009, 0x007, 0x0c0, 0x27b, 0x044, 0x29c, 0x001, + 0x044, 0x0e6, 0x001, 0x3c4, 0x30f, 0x22d, 0x044, 0x2f6, + 0x002, 0x009, 0x005, 0x044, 0x031, 0x008, 0x345, 0x21d, + 0x01c, 0x307, 0x21d, 0x304, 0x233, 0x001, 0x007, 0x3a7, + 0x071, 0x044, 0x1a9, 0x000, 0x3c5, 0x002, 0x026, 0x044, + 0x141, 0x001, 0x020, 0x283, 0x001, 0x055, 0x3c4, 0x3ef, + 0x027, 0x3c4, 0x3fd, 0x026, 0x364, 0x26f, 0x002, 0x001, + 0x008, 0x3c4, 0x3fd, 0x26f, 0x044, 0x290, 0x001, 0x344, + 0x21f, 0x01c, 0x3c4, 0x3bf, 0x200, 0x3c4, 0x39f, 0x2cf, + 0x0c0, 0x2d8, 0x0c0, 0x26b, 0x364, 0x234, 0x002, 0x009, + 0x012, 0x364, 0x33b, 0x007, 0x001, 0x00d, 0x044, 0x066, + 0x004, 0x364, 0x33c, 0x020, 0x009, 0x005, 0x044, 0x3b6, + 0x003, 0x054, 0x0a0, 0x081, 0x189, 0x020, 0x1a9, 0x000, + 0x044, 0x3fd, 0x000, 0x387, 0x3ff, 0x044, 0x02b, 0x001, + 0x3a7, 0x022, 0x020, 0x1bd, 0x000, 0x0a0, 0x081, 0x189, + 0x020, 0x1a9, 0x000, 0x080, 0x044, 0x02b, 0x001, 0x3b7, + 0x300, 0x387, 0x020, 0x044, 0x1a9, 0x000, 0x364, 0x024, + 0x002, 0x001, 0x006, 0x399, 0x305, 0x000, 0x004, 0x397, + 0x200, 0x044, 0x322, 0x001, 0x3a7, 0x022, 0x044, 0x1bd, + 0x000, 0x364, 0x232, 0x002, 0x001, 0x005, 0x044, 0x382, + 0x001, 0x000, 0x0c9, 0x3a7, 0x061, 0x044, 0x1bd, 0x000, + 0x0a5, 0x044, 0x1bd, 0x000, 0x3a7, 0x072, 0x044, 0x1bd, + 0x000, 0x3a7, 0x0f1, 0x044, 0x1bd, 0x000, 0x385, 0x004, + 0x0b1, 0x020, 0x1bd, 0x000, 0x364, 0x22c, 0x002, 0x009, + 0x2ac, 0x364, 0x234, 0x001, 0x001, 0x058, 0x020, 0x232, + 0x000, 0x3c4, 0x3fe, 0x027, 0x364, 0x234, 0x002, 0x001, + 0x04d, 0x000, 0x2cd, 0x3b7, 0x211, 0x044, 0x199, 0x000, + 0x384, 0x00f, 0x140, 0x239, 0x00b, 0x004, 0x385, 0x010, + 0x140, 0x237, 0x00b, 0x004, 0x385, 0x020, 0x044, 0x1bd, + 0x000, 0x307, 0x239, 0x00b, 0x004, 0x208, 0x101, 0x384, + 0x01f, 0x183, 0x327, 0x237, 0x00b, 0x004, 0x2a8, 0x121, + 0x3a4, 0x00f, 0x285, 0x184, 0x3c4, 0x01f, 0x238, 0x362, + 0x238, 0x017, 0x00b, 0x005, 0x0a1, 0x1ad, 0x285, 0x305, + 0x238, 0x32a, 0x238, 0x3a4, 0x008, 0x285, 0x3b7, 0x210, + 0x044, 0x1bd, 0x000, 0x347, 0x237, 0x23a, 0x347, 0x238, + 0x23c, 0x347, 0x239, 0x23b, 0x045, 0x345, 0x21c, 0x021, + 0x045, 0x308, 0x21c, 0x244, 0x021, 0x0c0, 0x240, 0x307, + 0x022, 0x384, 0x001, 0x245, 0x240, 0x142, 0x240, 0x364, + 0x240, 0x100, 0x009, 0x3eb, 0x0a1, 0x044, 0x0d9, 0x001, + 0x307, 0x240, 0x327, 0x022, 0x286, 0x384, 0x001, 0x001, + 0x3ee, 0x0a2, 0x307, 0x22b, 0x384, 0x003, 0x001, 0x008, + 0x0aa, 0x262, 0x003, 0x001, 0x003, 0x0a5, 0x289, 0x240, + 0x240, 0x387, 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+ 0x091, 0x382, 0x030, 0x001, 0x0a6, 0x3b7, 0x301, 0x044, + 0x192, 0x000, 0x384, 0x3c7, 0x385, 0x018, 0x044, 0x1bd, + 0x000, 0x3c4, 0x3f7, 0x024, 0x000, 0x0a4, 0x347, 0x24d, + 0x22b, 0x364, 0x233, 0x006, 0x001, 0x033, 0x307, 0x22b, + 0x364, 0x233, 0x002, 0x001, 0x023, 0x364, 0x233, 0x080, + 0x001, 0x00a, 0x307, 0x24d, 0x197, 0x384, 0x007, 0x044, + 0x3a4, 0x008, 0x364, 0x233, 0x100, 0x001, 0x00c, 0x307, + 0x24d, 0x19b, 0x384, 0x007, 0x385, 0x010, 0x044, 0x3a4, + 0x008, 0x3c4, 0x27f, 0x233, 0x000, 0x00b, 0x3c5, 0x003, + 0x22a, 0x197, 0x044, 0x39c, 0x008, 0x003, 0x298, 0x044, + 0x082, 0x00b, 0x0a2, 0x1ab, 0x324, 0x020, 0x021, 0x181, + 0x006, 0x045, 0x3b7, 0x301, 0x087, 0x044, 0x1b7, 0x000, + 0x3b7, 0x211, 0x082, 0x044, 0x1b7, 0x000, 0x3c4, 0x3f7, + 0x021, 0x000, 0x36c, 0x3b7, 0x301, 0x044, 0x192, 0x000, + 0x384, 0x3f8, 0x105, 0x044, 0x1bd, 0x000, 0x3b7, 0x211, + 0x082, 0x044, 0x1a9, 0x000, 0x3c5, 0x008, 0x021, 0x344, + 0x21f, 0x021, 0x3b7, 0x250, 0x088, 0x044, 0x1a9, 0x000, + 0x3b7, 0x211, 0x082, 0x044, 0x1a9, 0x000, 0x000, 0x347, + 0x3b7, 0x301, 0x387, 0x3c7, 0x044, 0x1b8, 0x000, 0x3a7, + 0x060, 0x083, 0x044, 0x1b7, 0x000, 0x3b7, 0x070, 0x083, + 0x18a, 0x044, 0x1b7, 0x000, 0x3c4, 0x3f7, 0x024, 0x000, + 0x36f, 0x3b7, 0x301, 0x044, 0x192, 0x000, 0x384, 0x3c7, + 0x385, 0x028, 0x044, 0x1bd, 0x000, 0x3c5, 0x048, 0x024, + 0x3a7, 0x060, 0x083, 0x044, 0x1a9, 0x000, 0x3b7, 0x070, + 0x083, 0x18a, 0x044, 0x1a9, 0x000, 0x000, 0x351, 0x307, + 0x22b, 0x284, 0x2a8, 0x2c4, 0x24d, 0x245, 0x24d, 0x2a8, + 0x045, 0x2f4, 0x200, 0x001, 0x008, 0x364, 0x2cf, 0x007, + 0x029, 0x1dc, 0x007, 0x287, 0x385, 0x300, 0x208, 0x001, + 0x04b, 0x364, 0x33b, 0x010, 0x029, 0x1dc, 0x007, 0x3c5, + 0x002, 0x00c, 0x287, 0x384, 0x0ff, 0x305, 0x21d, 0x1b7, + 0x2e4, 0x001, 0x001, 0x01d, 0x040, 0x384, 0x007, 0x117, + 0x001, 0x00c, 0x3c5, 0x040, 0x02d, 0x081, 0x044, 0x189, + 0x000, 0x3c4, 0x3bf, 0x02d, 0x042, 0x247, 0x029, 0x364, + 0x018, 0x001, 0x009, 0x005, 0x3c5, 0x010, 0x021, 0x2e4, + 0x002, 0x001, 0x017, 0x264, 0x080, 0x001, 0x005, 0x0a4, + 0x1a7, 0x285, 0x040, 0x3c5, 0x080, 0x02d, 0x081, 0x044, + 0x189, 0x000, 0x3c4, 0x37f, 0x02d, 0x042, 0x247, 0x02a, + 0x000, 0x014, 0x38e, 0x3ff, 0x1b8, 0x00a, 0x00a, 0x244, + 0x029, 0x3c4, 0x3ef, 0x021, 0x3c4, 0x3fd, 0x00c, 0x120, + 0x001, 0x004, 0x244, 0x02a, 0x020, 0x181, 0x006, 0x289, + 0x00a, 0x004, 0x2c7, 0x251, 0x22e, 0x364, 0x026, 0x001, + 0x021, 0x181, 0x006, 0x041, 0x3a4, 0x01f, 0x001, 0x005, + 0x044, 0x0d9, 0x001, 0x043, 0x1b7, 0x001, 0x005, 0x044, + 0x182, 0x000, 0x020, 0x181, 0x006, 0x2e4, 0x002, 0x009, + 0x01b, 0x3c4, 0x2ff, 0x232, 0x120, 0x001, 0x012, 0x3d5, + 0x300, 0x232, 0x044, 0x099, 0x00b, 0x32a, 0x026, 0x00a, + 0x008, 0x044, 0x20d, 0x000, 0x044, 0x232, 0x000, 0x020, + 0x181, 0x006, 0x042, 0x307, 0x240, 0x20a, 0x040, 0x020, + 0x181, 0x006, 0x289, 0x00a, 0x004, 0x2c7, 0x256, 0x22e, + 0x364, 0x026, 0x002, 0x021, 0x181, 0x006, 0x041, 0x3a4, + 0x01f, 0x001, 0x005, 0x044, 0x0de, 0x001, 0x043, 0x1b7, + 0x001, 0x005, 0x044, 0x0e2, 0x001, 0x020, 0x181, 0x006, + 0x364, 0x23f, 0x003, 0x009, 0x007, 0x044, 0x340, 0x001, + 0x247, 0x249, 0x054, 0x347, 0x249, 0x248, 0x2c7, 0x23f, + 0x083, 0x18a, 0x385, 0x018, 0x364, 0x23f, 0x001, 0x001, + 0x006, 0x245, 0x057, 0x000, 0x005, 0x208, 0x244, 0x057, + 0x087, 0x18c, 0x385, 0x0e0, 0x364, 0x23f, 0x002, 0x001, + 0x009, 0x245, 0x057, 0x044, 0x27d, 0x001, 0x000, 0x005, + 0x208, 0x244, 0x057, 0x020, 0x181, 0x006, 0x2c7, 0x246, + 0x3b7, 0x300, 0x044, 0x192, 0x000, 0x384, 0x33f, 0x327, + 0x246, 0x3a4, 0x0c0, 0x285, 0x3b7, 0x300, 0x044, 0x1bd, + 0x000, 0x3b7, 0x200, 0x044, 0x192, 0x000, 0x0a3, 0x1a9, + 0x2a8, 0x284, 0x040, 0x307, 0x246, 0x384, 0x030, 0x264, + 0x010, 0x001, 0x012, 0x040, 0x041, 0x3b7, 0x201, 0x044, + 0x192, 0x000, 0x384, 0x3e0, 0x385, 0x006, 0x044, 0x1bd, + 0x000, 0x043, 0x042, 0x185, 0x2a8, 0x284, 0x227, 0x042, + 0x285, 0x3b7, 0x200, 0x044, 0x1bd, 0x000, 0x307, 0x246, + 0x384, 0x007, 0x044, 0x375, 0x00b, 0x3a7, 0x073, 0x307, + 0x246, 0x184, 0x00a, 0x014, 0x044, 0x192, 0x000, 0x384, + 0x3e2, 0x327, 0x246, 0x1b5, 0x3a4, 0x01c, 0x285, 0x3a7, + 0x073, 0x044, 0x1bd, 0x000, 0x000, 0x006, 0x081, 0x044, + 0x1a9, 0x000, 0x020, 0x181, 0x006, 0x3c5, 0x001, 0x00c, + 0x187, 0x0a7, 0x1a7, 0x2a8, 0x324, 0x00c, 0x225, 0x2c7, + 0x00c, 0x045, 0x04e, 0x087, 0x011, 0x054, 0x084 + +}; /* end fm10000_serdes_spico_code_prd2 */ + + + +/* Spico Swap code (production version 2) + * source file: serdes.0x2055_0045.swap + * Note: if swap code exists, if must be loaded on top of + * the sbus master image. + */ + +const uint32_t fm10000_serdes_swap_code_version_build_id_prd2 = 0x20550045; +const uint32_t fm10000_serdes_swap_code_size_prd2 = 7842; + +const uint16_t fm10000_serdes_swap_code_prd2[] = { + 0x01e, 0x09d, 0x002, 0x000, 0x000, 0x008, 0x00f, 0x07b, + 0x020, 0x01e, 0x00f, 0x069, 0x01d, 0x029, 0x00b, 0x01d, + 0x02c, 0x382, 0x04e, 0x020, 0x23b, 0x009, 0x020, 0x28e, + 0x00a, 0x020, 0x03a, 0x00a, 0x020, 0x0fe, 0x00a, 0x020, + 0x3f3, 0x008, 0x020, 0x013, 0x009, 0x020, 0x075, 0x00a, + 0x0c1, 0x244, 0x3c5, 0x040, 0x245, 0x3c4, 0x3bf, 0x200, + 0x044, 0x172, 0x000, 0x020, 0x0d3, 0x000, 0x020, 0x2c3, + 0x008, 0x020, 0x375, 0x00b, 0x0c1, 0x201, 0x045, 0x020, + 0x04a, 0x009, 0x020, 0x04e, 0x009, 0x020, 0x256, 0x002, + 0x020, 0x17f, 0x009, 0x020, 0x23f, 0x006, 0x020, 0x285, + 0x00a, 0x020, 0x209, 0x00b, 0x020, 0x257, 0x006, 0x020, + 0x117, 0x008, 0x020, 0x394, 0x00a, 0x020, 0x048, 0x00b, + 0x020, 0x1dc, 0x007, 0x020, 0x27f, 0x00a, 0x020, 0x2d2, + 0x006, 0x020, 0x1e2, 0x007, 0x020, 0x295, 0x00b, 0x020, + 0x3a8, 0x001, 0x020, 0x277, 0x00b, 0x020, 0x2ba, 0x00b, + 0x020, 0x2d5, 0x006, 0x020, 0x326, 0x006, 0x020, 0x350, + 0x006, 0x020, 0x1dc, 0x007, 0x020, 0x35a, 0x006, 0x020, + 0x0a4, 0x00b, 0x020, 0x38e, 0x006, 0x020, 0x011, 0x007, + 0x020, 0x016, 0x007, 0x020, 0x31e, 0x007, 0x020, 0x324, + 0x007, 0x020, 0x3b6, 0x007, 0x020, 0x02a, 0x007, 0x020, + 0x041, 0x007, 0x020, 0x060, 0x007, 0x020, 0x06d, 0x007, + 0x020, 0x072, 0x007, 0x020, 0x2d1, 0x007, 0x020, 0x1dc, + 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, + 0x1dc, 0x007, 0x020, 0x252, 0x007, 0x020, 0x293, 0x007, + 0x020, 0x2d8, 0x00b, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, + 0x007, 0x020, 0x16f, 0x007, 0x020, 0x185, 0x007, 0x020, + 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, + 0x020, 0x1dc, 0x007, 0x020, 0x30e, 0x00b, 0x020, 0x1dc, + 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, + 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, + 0x020, 0x1dc, 0x007, 0x020, 0x1dc, 0x007, 0x020, 0x1dc, + 0x007, 0x020, 0x077, 0x007, 0x020, 0x0b1, 0x007, 0x020, + 0x103, 0x007, 0x020, 0x1c5, 0x008, 0x020, 0x1dc, 0x007, + 0x020, 0x168, 0x007, 0x287, 0x264, 0x004, 0x001, 0x049, + 0x3c5, 0x00c, 0x00c, 0x3c5, 0x020, 0x33b, 0x18e, 0x00a, + 0x013, 0x044, 0x04c, 0x004, 0x3a4, 0x001, 0x001, 0x014, + 0x364, 0x052, 0x001, 0x009, 0x093, 0x044, 0x0bc, 0x004, + 0x000, 0x08e, 0x3c4, 0x2ff, 0x053, 0x3c4, 0x030, 0x027, + 0x000, 0x3ec, 0x3c4, 0x3fe, 0x052, 0x000, 0x081, 0x043, + 0x327, 0x33b, 0x020, 0x1de, 0x007, 0x2e4, 0x080, 0x009, + 0x00d, 0x3d5, 0x220, 0x33c, 0x100, 0x009, 0x06e, 0x044, + 0x3b6, 0x003, 0x000, 0x06c, 0x3d5, 0x120, 0x33c, 0x100, + 0x009, 0x022, 0x044, 0x066, 0x004, 0x000, 0x061, 0x384, + 0x003, 0x3c4, 0x3df, 0x33b, 0x262, 0x003, 0x001, 0x3d9, + 0x3c4, 0x32d, 0x33c, 0x3c4, 0x3ef, 0x027, 0x2e4, 0x040, + 0x009, 0x3d5, 0x100, 0x009, 0x007, 0x044, 0x063, 0x004, + 0x000, 0x046, 0x364, 0x200, 0x004, 0x029, 0x1dc, 0x007, + 0x0c0, 0x2d8, 0x111, 0x001, 0x028, 0x3c5, 0x002, 0x33c, + 0x3c5, 0x001, 0x33b, 0x344, 0x21f, 0x33c, 0x287, 0x19b, + 0x247, 0x361, 0x287, 0x183, 0x19b, 0x247, 0x360, 0x0c0, + 0x35e, 0x2e4, 0x020, 0x001, 0x004, 0x0c5, 0x35e, 0x2e4, + 0x010, 0x001, 0x005, 0x3c5, 0x080, 0x33c, 0x289, 0x384, + 0x010, 0x245, 0x33c, 0x044, 0x001, 0x004, 0x364, 0x33c, + 0x002, 0x001, 0x005, 0x3c5, 0x004, 0x200, 0x364, 0x33c, + 0x020, 0x009, 0x005, 0x044, 0x097, 0x004, 0x020, 0x181, + 0x006, 0x287, 0x19b, 0x11d, 0x001, 0x002, 0x287, 0x1a3, + 0x1b3, 0x19b, 0x180, 0x390, 0x1d7, 0x040, 0x199, 0x390, + 0x008, 0x040, 0x045, 0x000, 0x021, 0x000, 0x073, 0x000, + 0x05f, 0x000, 0x023, 0x000, 0x025, 0x000, 0x033, 0x000, + 0x035, 0x000, 0x037, 0x000, 0x041, 0x000, 0x01f, 0x000, + 0x021, 0x000, 0x023, 0x000, 0x031, 0x000, 0x082, 0x000, + 0x002, 0x020, 0x1dc, 0x007, 0x044, 0x378, 0x003, 0x3c4, + 0x3fd, 0x233, 0x000, 0x072, 0x2c7, 0x363, 0x000, 0x06e, + 0x2c7, 0x362, 0x000, 0x06a, 0x2c7, 0x341, 0x000, 0x066, + 0x2c7, 0x33f, 0x000, 0x062, 0x2c7, 0x340, 0x000, 0x05e, + 0x2c7, 0x344, 0x000, 0x05a, 0x2c7, 0x342, 0x000, 0x056, + 0x2c7, 0x343, 0x000, 0x052, 0x2c7, 0x341, 0x2c7, 0x33f, + 0x2c7, 0x340, 0x000, 0x04a, 0x307, 0x340, 0x300, 0x341, + 0x300, 0x33f, 0x282, 0x007, 0x006, 0x2c7, 0x23e, 0x000, + 0x03d, 0x043, 0x0a1, 0x020, 0x1de, 0x007, 0x287, 0x384, + 0x003, 0x181, 0x3c4, 0x3f3, 0x052, 0x245, 0x052, 0x3a4, + 0x00c, 0x3c4, 0x3f3, 0x33c, 0x2c5, 0x33c, 0x000, 0x026, + 0x3c5, 0x002, 0x233, 0x3c7, 0x3ff, 0x352, 0x3c7, 0x3ff, + 0x353, 0x1d3, 0x353, 0x0cf, 0x354, 0x1cb, 0x354, 0x3c5, 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0x014, 0x38e, 0x3ff, 0x1b8, + 0x00a, 0x00a, 0x244, 0x029, 0x3c4, 0x3ef, 0x021, 0x3c4, + 0x3fd, 0x00c, 0x120, 0x001, 0x004, 0x244, 0x02a, 0x020, + 0x181, 0x006, 0x364, 0x23f, 0x003, 0x009, 0x007, 0x044, + 0x340, 0x001, 0x247, 0x249, 0x054, 0x347, 0x249, 0x248, + 0x2c7, 0x23f, 0x083, 0x18a, 0x385, 0x018, 0x364, 0x23f, + 0x001, 0x001, 0x006, 0x245, 0x057, 0x000, 0x005, 0x208, + 0x244, 0x057, 0x087, 0x18c, 0x385, 0x0e0, 0x364, 0x23f, + 0x002, 0x001, 0x009, 0x245, 0x057, 0x044, 0x27d, 0x001, + 0x000, 0x005, 0x208, 0x244, 0x057, 0x020, 0x181, 0x006, + 0x04e, 0x0ce, 0x045, 0x03c, 0x0f5, 0x04e, 0x0fd, 0x07e, + 0x00a, 0x0f9 + +}; /* end fm10000_serdes_swap_code_prd2 */ diff --git a/drivers/net/fm10k/switch/fm10k_spico_code.h b/drivers/net/fm10k/switch/fm10k_spico_code.h new file mode 100644 index 0000000..c172638 --- /dev/null +++ b/drivers/net/fm10k/switch/fm10k_spico_code.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2019 Silicom Ltd. Connectivity Solutions + */ + +#ifndef _FM10K_SPICO_CODE_H_ +#define _FM10K_SPICO_CODE_H_ +#include + +extern const uint32_t fm10000_sbus_master_code_version_build_id_prd; +extern const uint32_t fm10000_sbus_master_code_size_prd; +extern const uint16_t fm10000_sbus_master_code_prd[]; + +extern const uint32_t fm10000_serdes_spico_code_version_build_id_prd2; +extern const uint32_t fm10000_serdes_spico_code_size_prd2; +extern const uint16_t fm10000_serdes_spico_code_prd2[]; + +extern const uint32_t fm10000_serdes_swap_code_version_build_id_prd2; +extern const uint32_t fm10000_serdes_swap_code_size_prd2; +extern const uint16_t fm10000_serdes_swap_code_prd2[]; + +#endif /* _FM10K_SPICO_CODE_H_ */