net/mlx5: fix legacy inline multi-packet performance
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Commit Message
The legacy multi-packet write is the feature allowing to
put multiple packets into one transmitting descriptor,
this feature is supported by only NIC ConnectX-4LX.
The number of packets should be limited to provide
optimal size descriptor and better performance.
Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
drivers/net/mlx5/mlx5_prm.h | 1 +
drivers/net/mlx5/mlx5_rxtx.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
Comments
From: Viacheslav Ovsiienko
> The legacy multi-packet write is the feature allowing to put multiple packets
> into one transmitting descriptor, this feature is supported by only NIC
> ConnectX-4LX.
> The number of packets should be limited to provide optimal size descriptor
> and better performance.
>
> Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
27/11/2019 14:54, Matan Azrad:
> From: Viacheslav Ovsiienko
> > The legacy multi-packet write is the feature allowing to put multiple packets
> > into one transmitting descriptor, this feature is supported by only NIC
> > ConnectX-4LX.
> > The number of packets should be limited to provide optimal size descriptor
> > and better performance.
> >
> > Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
> >
> > Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> Acked-by: Matan Azrad <matan@mellanox.com>
Applied, thanks
From: Viacheslav Ovsiienko
> The legacy multi-packet write is the feature allowing to put multiple packets
> into one transmitting descriptor, this feature is supported by only NIC
> ConnectX-4LX.
> The number of packets should be limited to provide optimal size descriptor
> and better performance.
>
> Fixes: 18a1c20044c0 ("net/mlx5: implement Tx burst template")
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
@@ -100,6 +100,7 @@
*/
#define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
#define MLX5_MPW_MAX_PACKETS 6
+#define MLX5_MPW_INLINE_MAX_PACKETS 2
/*
* Default packet length threshold to be inlined with
@@ -4059,7 +4059,9 @@ enum mlx5_txcmp_code {
* Limits the amount of packets in one WQE
* to improve CQE latency generation.
*/
- nlim = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
+ nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
+ MLX5_MPW_INLINE_MAX_PACKETS :
+ MLX5_EMPW_MAX_PACKETS);
/* Check whether we have minimal amount WQEs */
if (unlikely(loc->wqe_free <
((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))