From patchwork Tue Oct 1 14:36:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simei Su X-Patchwork-Id: 60346 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B80CC1B9A9; Tue, 1 Oct 2019 16:36:28 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 5681D4CA6 for ; Tue, 1 Oct 2019 16:36:26 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Oct 2019 07:36:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,571,1559545200"; d="scan'208";a="221019887" Received: from npg-dpdk-cvl-simeisu-118d193.sh.intel.com ([10.67.110.183]) by fmsmga002.fm.intel.com with ESMTP; 01 Oct 2019 07:36:24 -0700 From: Simei Su To: qi.z.zhang@intel.com, xiaolong.ye@intel.com, ferruh.yigit@intel.com Cc: dev@dpdk.org, simei.su@intel.com Date: Tue, 1 Oct 2019 22:36:03 +0800 Message-Id: <1569940564-311988-3-git-send-email-simei.su@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1569940564-311988-1-git-send-email-simei.su@intel.com> References: <1569740956-69634-1-git-send-email-simei.su@intel.com> <1569940564-311988-1-git-send-email-simei.su@intel.com> Subject: [dpdk-dev] [PATCH v8 2/3] ethdev: extend RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch reserves several bits as input set selection from the high end of the 64 bits. It is combined with exisiting ETH_RSS_* to represent RSS types. Signed-off-by: Simei Su Reviewed-by: Qi Zhang Acked-by: Ori Kam --- lib/librte_ethdev/rte_ethdev.c | 22 ++++++++++++++++++++++ lib/librte_ethdev/rte_ethdev.h | 14 ++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/lib/librte_ethdev/rte_ethdev.c b/lib/librte_ethdev/rte_ethdev.c index af82360..5e5a974 100644 --- a/lib/librte_ethdev/rte_ethdev.c +++ b/lib/librte_ethdev/rte_ethdev.c @@ -1269,6 +1269,17 @@ struct rte_eth_dev * goto rollback; } + /* simplified the SRC/DST_ONLY RSS offload modificaiton */ + if (dev_conf->rx_adv_conf.rss_conf.rss_hf & ETH_RSS_L3_SRC_ONLY && + dev_conf->rx_adv_conf.rss_conf.rss_hf & ETH_RSS_L3_DST_ONLY) + dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf &= + ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY); + + if (dev_conf->rx_adv_conf.rss_conf.rss_hf & ETH_RSS_L4_SRC_ONLY && + dev_conf->rx_adv_conf.rss_conf.rss_hf & ETH_RSS_L4_DST_ONLY) + dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf &= + ~(ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY); + /* Check that device supports requested rss hash functions. */ if ((dev_info.flow_type_rss_offloads | dev_conf->rx_adv_conf.rss_conf.rss_hf) != @@ -3112,6 +3123,17 @@ struct rte_eth_dev * if (ret != 0) return ret; + /* simplified the SRC/DST_ONLY RSS offload modificaiton */ + if (rss_conf->rss_hf & ETH_RSS_L3_SRC_ONLY && + rss_conf->rss_hf & ETH_RSS_L3_DST_ONLY) + rss_conf->rss_hf &= + ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY); + + if (rss_conf->rss_hf & ETH_RSS_L4_SRC_ONLY && + rss_conf->rss_hf & ETH_RSS_L4_DST_ONLY) + rss_conf->rss_hf &= + ~(ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY); + dev = &rte_eth_devices[port_id]; if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) != dev_info.flow_type_rss_offloads) { diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h index 7722f70..6d61b84 100644 --- a/lib/librte_ethdev/rte_ethdev.h +++ b/lib/librte_ethdev/rte_ethdev.h @@ -505,6 +505,20 @@ struct rte_eth_rss_conf { #define ETH_RSS_GENEVE (1ULL << 20) #define ETH_RSS_NVGRE (1ULL << 21) +/* + * We use the following macros to combine with above ETH_RSS_* for + * more specific input set selection. These bits are defined starting + * from the high end of the 64 bits. + * Note: If we use above ETH_RSS_* without SRC/DST_ONLY, it represents + * both SRC and DST are taken into account. If SRC_ONLY and DST_ONLY of + * the same level be used simultaneously, it is the same case as none of + * them are added. + */ +#define ETH_RSS_L3_SRC_ONLY (1ULL << 63) +#define ETH_RSS_L3_DST_ONLY (1ULL << 62) +#define ETH_RSS_L4_SRC_ONLY (1ULL << 61) +#define ETH_RSS_L4_DST_ONLY (1ULL << 60) + #define ETH_RSS_IP ( \ ETH_RSS_IPV4 | \ ETH_RSS_FRAG_IPV4 | \