From patchwork Mon Jun 10 07:38:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 54588 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C643B1BEAE; Mon, 10 Jun 2019 09:39:05 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id EEC671BE93 for ; Mon, 10 Jun 2019 09:38:54 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us5.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id CE53F4C0058 for ; Mon, 10 Jun 2019 07:38:53 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 10 Jun 2019 00:38:50 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 10 Jun 2019 00:38:50 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id x5A7cn2i008773; Mon, 10 Jun 2019 08:38:49 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 55B821616E0; Mon, 10 Jun 2019 08:38:49 +0100 (BST) From: Andrew Rybchenko To: CC: Richard Houldsworth Date: Mon, 10 Jun 2019 08:38:23 +0100 Message-ID: <1560152324-20538-9-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1560152324-20538-1-git-send-email-arybchenko@solarflare.com> References: <1560152324-20538-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24664.003 X-TM-AS-Result: No-6.869400-4.000000-10 X-TMASE-MatchedRID: ShoIsLLl1JQazpITYEAiViyKzJY7d2nbOtlHh2+ppE/I9EDAP/dptsiT Wug2C4DN3iuNqik9NLywgcHDNo5AtCHhSBQfglfsA9lly13c/gEisyg/lfGoZ0dmDSBYfnJRl5w rogyz/gNEj+W35/xeauMAObeva31zf0wwpICCAZZZMZ6MZ0H1Ukrh/hn4JkBnO3tmMk8BUiIGs/ +hIg7uQVsxdzBtwMhqgDLqnrRlXrZ8nn9tnqel2DsAVzN+Ov/sa5uO9XwJCw2tM9abO572jS202 WYoOcmwGiTv9d6KTfFVWpp9hvKrgA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--6.869400-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24664.003 X-MDID: 1560152334-9hMuMLBa5zd8 Subject: [dpdk-dev] [PATCH 08/29] net/sfc/base: add extensible NVRAM info function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Richard Houldsworth Includes the partition read-only flag, to allow for checks before opening the partition. Signed-off-by: Richard Houldsworth Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/efx.h | 10 ++++++ drivers/net/sfc/base/efx_impl.h | 6 ++++ drivers/net/sfc/base/efx_nvram.c | 66 +++++++++++++++++++++++++++++++--------- 3 files changed, 68 insertions(+), 14 deletions(-) diff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h index 879bc8d..a5342af 100644 --- a/drivers/net/sfc/base/efx.h +++ b/drivers/net/sfc/base/efx.h @@ -1606,6 +1606,16 @@ enum { EFX_NVRAM_NTYPES, } efx_nvram_type_t; +typedef struct efx_nvram_info_s { + uint32_t eni_flags; + uint32_t eni_partn_size; + uint32_t eni_address; + uint32_t eni_erase_size; + uint32_t eni_write_size; +} efx_nvram_info_t; + +#define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) + extern __checkReturn efx_rc_t efx_nvram_init( __in efx_nic_t *enp); diff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h index b5ac84d..684403f 100644 --- a/drivers/net/sfc/base/efx_impl.h +++ b/drivers/net/sfc/base/efx_impl.h @@ -568,6 +568,12 @@ __out_opt uint32_t *write_sizep); __checkReturn efx_rc_t +efx_mcdi_nvram_info_ex( + __in efx_nic_t *enp, + __in uint32_t partn, + __out efx_nvram_info_t *eni); + + __checkReturn efx_rc_t efx_mcdi_nvram_update_start( __in efx_nic_t *enp, __in uint32_t partn); diff --git a/drivers/net/sfc/base/efx_nvram.c b/drivers/net/sfc/base/efx_nvram.c index 5c611c3..df7e851 100644 --- a/drivers/net/sfc/base/efx_nvram.c +++ b/drivers/net/sfc/base/efx_nvram.c @@ -657,13 +657,10 @@ } __checkReturn efx_rc_t -efx_mcdi_nvram_info( +efx_mcdi_nvram_info_ex( __in efx_nic_t *enp, __in uint32_t partn, - __out_opt size_t *sizep, - __out_opt uint32_t *addressp, - __out_opt uint32_t *erase_sizep, - __out_opt uint32_t *write_sizep) + __out efx_nvram_info_t *enip) { EFX_MCDI_DECLARE_BUF(payload, MC_CMD_NVRAM_INFO_IN_LEN, MC_CMD_NVRAM_INFO_V2_OUT_LEN); @@ -690,21 +687,26 @@ goto fail2; } - if (sizep) - *sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_SIZE); + enip->eni_partn_size = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_SIZE); - if (addressp) - *addressp = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_PHYSADDR); + enip->eni_address = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_PHYSADDR); - if (erase_sizep) - *erase_sizep = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_ERASESIZE); + enip->eni_erase_size = MCDI_OUT_DWORD(req, NVRAM_INFO_OUT_ERASESIZE); - if (write_sizep) { - *write_sizep = + enip->eni_write_size = (req.emr_out_length_used < MC_CMD_NVRAM_INFO_V2_OUT_LEN) ? 0 : MCDI_OUT_DWORD(req, NVRAM_INFO_V2_OUT_WRITESIZE); - } + + enip->eni_flags = 0; + + if (MCDI_OUT_DWORD_FIELD(req, NVRAM_INFO_OUT_FLAGS, + NVRAM_INFO_OUT_PROTECTED)) + enip->eni_flags |= EFX_NVRAM_FLAG_READ_ONLY; + + if (MCDI_OUT_DWORD_FIELD(req, NVRAM_INFO_OUT_FLAGS, + NVRAM_INFO_OUT_READ_ONLY)) + enip->eni_flags |= EFX_NVRAM_FLAG_READ_ONLY; return (0); @@ -716,6 +718,42 @@ return (rc); } + __checkReturn efx_rc_t +efx_mcdi_nvram_info( + __in efx_nic_t *enp, + __in uint32_t partn, + __out_opt size_t *sizep, + __out_opt uint32_t *addressp, + __out_opt uint32_t *erase_sizep, + __out_opt uint32_t *write_sizep) +{ + efx_nvram_info_t eni; + efx_rc_t rc; + + if ((rc = efx_mcdi_nvram_info_ex(enp, partn, &eni)) != 0) + goto fail1; + + if (sizep) + *sizep = eni.eni_partn_size; + + if (addressp) + *addressp = eni.eni_address; + + if (erase_sizep) + *erase_sizep = eni.eni_erase_size; + + if (write_sizep) + *write_sizep = eni.eni_write_size; + + return (0); + +fail1: + EFSYS_PROBE1(fail1, efx_rc_t, rc); + + return (rc); +} + + /* * MC_CMD_NVRAM_UPDATE_START_V2 must be used to support firmware-verified * NVRAM updates. Older firmware will ignore the flags field in the request.