diff mbox series

[v3] net/ixgbe: fix multicast table enable error for VF

Message ID 1546839569-13787-1-git-send-email-wei.zhao1@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series [v3] net/ixgbe: fix multicast table enable error for VF |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/mellanox-Performance-Testing success Performance Testing PASS
ci/intel-Performance-Testing success Performance Testing PASS
ci/Intel-compilation success Compilation OK

Commit Message

Zhao1, Wei Jan. 7, 2019, 5:39 a.m. UTC 
  In ixgbe PMD code, all vf ars set with bit IXGBE_VMOLR_ROMPE,
which make vf accept packets that match the MTA table,
if some vf update IXGBE_MTA in function ixgbe_vf_set_multicast,
then all vf will receive packets from these address.
So there is need to set VMOLR register bit ROPE only after this
vf has been set multicast address. If this bit is set when pf host doing
initialization, this vf will receive multicast packets with address
written in MTA table.And also disable MTA when detect
all zero MAC address configuration from vf.
Align to ixgbe pf kernel 5.3.7 code to fix this bug.

Fixes: 00e30184daa0 ("ixgbe: add PF support")

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>

---

v2:
change patch name and fix typo in log.

v3:
fix typo and disable MTA when detect
all zero MAC address configuration.
---
 drivers/net/ixgbe/ixgbe_pf.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/ixgbe/ixgbe_pf.c b/drivers/net/ixgbe/ixgbe_pf.c
index 4b833ff..392e4a1 100644
--- a/drivers/net/ixgbe/ixgbe_pf.c
+++ b/drivers/net/ixgbe/ixgbe_pf.c
@@ -351,7 +351,7 @@  ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
 	int rar_entry = hw->mac.num_rar_entries - (vf + 1);
 	uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
 
-	vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
+	vmolr |= (IXGBE_VMOLR_ROPE |
 			IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
 	IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
 
@@ -503,6 +503,7 @@  ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 	const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
 	uint32_t reg_val;
 	int i;
+	u32 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
 
 	/* Disable multicast promiscuous first */
 	ixgbe_disable_vf_mc_promisc(dev, vf);
@@ -516,6 +517,12 @@  ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 		vfinfo->vf_mc_hashes[i] = hash_list[i];
 	}
 
+	if (nb_entries == 1 && !vfinfo->vf_mc_hashes[0]) {
+		vmolr &= ~IXGBE_VMOLR_ROMPE;
+		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
+		return 0;
+	}
+
 	for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
 		mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
 				& IXGBE_MTA_INDEX_MASK;
@@ -525,6 +532,9 @@  ixgbe_vf_set_multicast(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
 		IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
 	}
 
+	vmolr |= IXGBE_VMOLR_ROMPE;
+	IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
+
 	return 0;
 }