diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 7e3bad0..2437159 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -19,6 +19,8 @@
 static void ice_dev_stop(struct rte_eth_dev *dev);
 static void ice_dev_close(struct rte_eth_dev *dev);
 static int ice_dev_reset(struct rte_eth_dev *dev);
+static void ice_dev_info_get(struct rte_eth_dev *dev,
+			     struct rte_eth_dev_info *dev_info);
 
 static const struct rte_pci_id pci_id_ice_map[] = {
 	{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
@@ -41,6 +43,7 @@
 	.rx_queue_release             = ice_rx_queue_release,
 	.tx_queue_setup               = ice_tx_queue_setup,
 	.tx_queue_release             = ice_tx_queue_release,
+	.dev_infos_get                = ice_dev_info_get,
 };
 
 static void
@@ -843,3 +846,123 @@ static int ice_init_rss(struct ice_pf *pf)
 
 	return 0;
 }
+
+static void
+ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
+{
+	struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
+	struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct ice_vsi *vsi = pf->main_vsi;
+	struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
+
+	dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
+	dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
+	dev_info->max_rx_queues = vsi->nb_qps;
+	dev_info->max_tx_queues = vsi->nb_qps;
+	dev_info->max_mac_addrs = vsi->max_macaddrs;
+	dev_info->max_vfs = pci_dev->max_vfs;
+
+	dev_info->rx_offload_capa =
+		DEV_RX_OFFLOAD_VLAN_STRIP |
+		DEV_RX_OFFLOAD_IPV4_CKSUM |
+		DEV_RX_OFFLOAD_UDP_CKSUM |
+		DEV_RX_OFFLOAD_TCP_CKSUM |
+		DEV_RX_OFFLOAD_QINQ_STRIP |
+		DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+		DEV_RX_OFFLOAD_VLAN_EXTEND |
+		DEV_RX_OFFLOAD_JUMBO_FRAME;
+	dev_info->tx_offload_capa =
+		DEV_TX_OFFLOAD_VLAN_INSERT |
+		DEV_TX_OFFLOAD_QINQ_INSERT |
+		DEV_TX_OFFLOAD_IPV4_CKSUM |
+		DEV_TX_OFFLOAD_UDP_CKSUM |
+		DEV_TX_OFFLOAD_TCP_CKSUM |
+		DEV_TX_OFFLOAD_SCTP_CKSUM |
+		DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+		DEV_TX_OFFLOAD_TCP_TSO;
+	dev_info->rx_queue_offload_capa = 0;
+	dev_info->tx_queue_offload_capa = 0;
+
+	dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
+	dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
+	dev_info->flow_type_rss_offloads = ICE_RSS_OFFLOAD_ALL;
+
+	dev_info->default_rxconf = (struct rte_eth_rxconf) {
+		.rx_thresh = {
+			.pthresh = ICE_DEFAULT_RX_PTHRESH,
+			.hthresh = ICE_DEFAULT_RX_HTHRESH,
+			.wthresh = ICE_DEFAULT_RX_WTHRESH,
+		},
+		.rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
+		.rx_drop_en = 0,
+		.offloads = 0,
+	};
+
+	dev_info->default_txconf = (struct rte_eth_txconf) {
+		.tx_thresh = {
+			.pthresh = ICE_DEFAULT_TX_PTHRESH,
+			.hthresh = ICE_DEFAULT_TX_HTHRESH,
+			.wthresh = ICE_DEFAULT_TX_WTHRESH,
+		},
+		.tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
+		.tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
+		.offloads = 0,
+	};
+
+	dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
+		.nb_max = ICE_MAX_RING_DESC,
+		.nb_min = ICE_MIN_RING_DESC,
+		.nb_align = ICE_ALIGN_RING_DESC,
+	};
+
+	dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
+		.nb_max = ICE_MAX_RING_DESC,
+		.nb_min = ICE_MIN_RING_DESC,
+		.nb_align = ICE_ALIGN_RING_DESC,
+	};
+
+	switch (hw->port_info->phy.link_info.link_speed) {
+	case ICE_AQ_LINK_SPEED_10MB:
+		dev_info->speed_capa = ETH_LINK_SPEED_10M;
+		break;
+	case ICE_AQ_LINK_SPEED_100MB:
+		dev_info->speed_capa = ETH_LINK_SPEED_100M;
+		break;
+	case ICE_AQ_LINK_SPEED_1000MB:
+		dev_info->speed_capa = ETH_LINK_SPEED_1G;
+		break;
+	case ICE_AQ_LINK_SPEED_2500MB:
+		dev_info->speed_capa = ETH_LINK_SPEED_2_5G;
+		break;
+	case ICE_AQ_LINK_SPEED_5GB:
+		dev_info->speed_capa = ETH_LINK_SPEED_5G;
+		break;
+	case ICE_AQ_LINK_SPEED_10GB:
+		dev_info->speed_capa = ETH_LINK_SPEED_10G;
+		break;
+	case ICE_AQ_LINK_SPEED_20GB:
+		dev_info->speed_capa = ETH_LINK_SPEED_20G;
+		break;
+	case ICE_AQ_LINK_SPEED_25GB:
+		dev_info->speed_capa = ETH_LINK_SPEED_25G;
+		break;
+	case ICE_AQ_LINK_SPEED_40GB:
+		dev_info->speed_capa = ETH_LINK_SPEED_40G;
+		break;
+	case ICE_AQ_LINK_SPEED_UNKNOWN:
+	default:
+		PMD_DRV_LOG(ERR, "Unknown link speed");
+		dev_info->speed_capa = ETH_LINK_SPEED_AUTONEG;
+		break;
+	}
+
+	dev_info->nb_rx_queues = dev->data->nb_rx_queues;
+	dev_info->nb_tx_queues = dev->data->nb_tx_queues;
+
+	dev_info->default_rxportconf.burst_size = 32;
+	dev_info->default_txportconf.burst_size = 32;
+	dev_info->default_rxportconf.nb_queues = 1;
+	dev_info->default_txportconf.nb_queues = 1;
+	dev_info->default_rxportconf.ring_size = 1024;
+	dev_info->default_txportconf.ring_size = 1024;
+}
