[v3,1/4] config: use one single config option for C11 memory model
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Commit Message
Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
model, so all modules can leverage C11 atomic extension by enable this
option.
Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
Reviewed-by: Gavin Hu <Gavin.Hu@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
config/arm/meson.build | 2 +-
config/common_armv8a_linuxapp | 2 +-
config/common_base | 2 +-
config/defconfig_arm64-thunderx-linuxapp-gcc | 2 +-
lib/librte_ring/rte_ring.h | 4 ++--
5 files changed, 6 insertions(+), 6 deletions(-)
Comments
On 10/8/2018 10:11 AM, phil.yang@arm.com wrote:
> Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
> model, so all modules can leverage C11 atomic extension by enable this
> option.
>
> Signed-off-by: Phil Yang <phil.yang@arm.com>
> Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Reviewed-by: Gavin Hu <Gavin.Hu@arm.com>
> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
For series,
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Are you planning to send a new version to include the clean up, or get this one
first an do the cleanup on top of it? I think both are OK but please let us know.
And if there will be a new version with cleanup, please keep the review tag.
> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@intel.com>
> Sent: Wednesday, October 10, 2018 10:48 PM
> To: Phil Yang (Arm Technology China) <Phil.Yang@arm.com>; dev@dpdk.org
> Cc: jerin.jacob@caviumnetworks.com; Gavin Hu (Arm Technology China)
> <Gavin.Hu@arm.com>; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; Ola Liljedahl <Ola.Liljedahl@arm.com>
> Subject: Re: [PATCH v3 1/4] config: use one single config option for C11 memory
> model
>
> On 10/8/2018 10:11 AM, phil.yang@arm.com wrote:
> > Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
> > model, so all modules can leverage C11 atomic extension by enable this
> > option.
> >
> > Signed-off-by: Phil Yang <phil.yang@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> > Reviewed-by: Gavin Hu <Gavin.Hu@arm.com>
> > Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
>
> For series,
> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
>
> Are you planning to send a new version to include the clean up, or get this one
> first an do the cleanup on top of it? I think both are OK but please let us know.
> And if there will be a new version with cleanup, please keep the review tag.
Hi Ferruh,
Thanks for your remind.
I think it is better to merge this series first. Because the cleanup patch won't block any functionality.
I will do it on top of this series.
Thanks
Phil Yang
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10/10/2018 16:48, Ferruh Yigit:
> On 10/8/2018 10:11 AM, phil.yang@arm.com wrote:
> > Keep only single config option RTE_USE_C11_MEM_MODEL for C11 memory
> > model, so all modules can leverage C11 atomic extension by enable this
> > option.
> >
> > Signed-off-by: Phil Yang <phil.yang@arm.com>
> > Reviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> > Reviewed-by: Gavin Hu <Gavin.Hu@arm.com>
> > Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
>
> For series,
> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Series applied, thanks
@@ -53,7 +53,7 @@ flags_cavium = [
['RTE_MAX_NUMA_NODES', 2],
['RTE_MAX_LCORE', 96],
['RTE_MAX_VFIO_GROUPS', 128],
- ['RTE_RING_USE_C11_MEM_MODEL', false]]
+ ['RTE_USE_C11_MEM_MODEL', false]]
flags_dpaa = [
['RTE_MACHINE', '"dpaa"'],
['RTE_CACHE_LINE_SIZE', 64],
@@ -29,7 +29,7 @@ CONFIG_RTE_ARCH_ARM64_MEMCPY=n
#CONFIG_RTE_ARM64_MEMCPY_ALIGN_MASK=0xF
#CONFIG_RTE_ARM64_MEMCPY_STRICT_ALIGN=n
-CONFIG_RTE_RING_USE_C11_MEM_MODEL=y
+CONFIG_RTE_USE_C11_MEM_MODEL=y
CONFIG_RTE_LIBRTE_FM10K_PMD=n
CONFIG_RTE_LIBRTE_SFC_EFX_PMD=n
@@ -661,7 +661,7 @@ CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
# Compile librte_ring
#
CONFIG_RTE_LIBRTE_RING=y
-CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
+CONFIG_RTE_USE_C11_MEM_MODEL=n
#
# Compile librte_mempool
@@ -10,7 +10,7 @@ CONFIG_RTE_CACHE_LINE_SIZE=128
CONFIG_RTE_MAX_NUMA_NODES=2
CONFIG_RTE_MAX_LCORE=96
CONFIG_RTE_MAX_VFIO_GROUPS=128
-CONFIG_RTE_RING_USE_C11_MEM_MODEL=n
+CONFIG_RTE_USE_C11_MEM_MODEL=n
#
# Compile PMD for octeontx sso event device
@@ -303,11 +303,11 @@ void rte_ring_dump(FILE *f, const struct rte_ring *r);
* There are 2 choices for the users
* 1.use rmb() memory barrier
* 2.use one-direcion load_acquire/store_release barrier,defined by
- * CONFIG_RTE_RING_USE_C11_MEM_MODEL=y
+ * CONFIG_RTE_USE_C11_MEM_MODEL=y
* It depends on performance test results.
* By default, move common functions to rte_ring_generic.h
*/
-#ifdef RTE_RING_USE_C11_MEM_MODEL
+#ifdef RTE_USE_C11_MEM_MODEL
#include "rte_ring_c11_mem.h"
#else
#include "rte_ring_generic.h"