From patchwork Mon Sep 24 13:50:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 45206 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D35D84CA6; Mon, 24 Sep 2018 15:51:00 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [148.163.129.52]) by dpdk.org (Postfix) with ESMTP id 2A4792C0C for ; Mon, 24 Sep 2018 15:50:51 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id ED78CB40087 for ; Mon, 24 Sep 2018 13:50:49 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 24 Sep 2018 06:50:47 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Mon, 24 Sep 2018 06:50:46 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id w8ODojFH014505; Mon, 24 Sep 2018 14:50:45 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 94C7C1626D1; Mon, 24 Sep 2018 14:50:45 +0100 (BST) From: Andrew Rybchenko To: CC: Richard Houldsworth Date: Mon, 24 Sep 2018 14:50:23 +0100 Message-ID: <1537797030-26548-5-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1537797030-26548-1-git-send-email-arybchenko@solarflare.com> References: <1537797030-26548-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24114.005 X-TM-AS-Result: No-3.142900-4.000000-10 X-TMASE-MatchedRID: uNRHijKOwlR+QvaEhAITJwPZZctd3P4BWjWsWQUWzVovM0Gdq0fzqfG3 99+Ui/tdiF9KmMbK/I+CIKiKLiTT+5Coy9iDotiw58dk5sbwmyj4bPjfm0hIQVubJMtFY5Lxo8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtRsgw6nelu9fM4NvIF1Hhq5Kxde0nDrh4tADwpjmiPnI8Gk kKDn7rx7elExnRvHvQeNycEXBh29qlHx5eV5O3IHA0V3BXonbchdeYev6ImzWyrFieOBrhBjzcW rt/fwYrRcB2ZpPnVjJuI9MGG9suFpRMZUCEHkRt X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.142900-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24114.005 X-MDID: 1537797050-b8jaUeFWOIfa Subject: [dpdk-dev] [PATCH 04/11] net/sfc/base: update to current port mode terminology X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Richard Houldsworth From Medford onwards, the newer constants enumerating port modes should be used. Signed-off-by: Richard Houldsworth Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/ef10_nic.c | 41 ++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c index b54cd3940..c3634e351 100644 --- a/drivers/net/sfc/base/ef10_nic.c +++ b/drivers/net/sfc/base/ef10_nic.c @@ -135,26 +135,29 @@ ef10_nic_get_port_mode_bandwidth( efx_rc_t rc; switch (port_mode) { - case TLV_PORT_MODE_10G: + case TLV_PORT_MODE_1x1_NA: /* mode 0 */ bandwidth = 10000; break; - case TLV_PORT_MODE_10G_10G: + case TLV_PORT_MODE_1x1_1x1: /* mode 2 */ bandwidth = 10000 * 2; break; - case TLV_PORT_MODE_10G_10G_10G_10G: - case TLV_PORT_MODE_10G_10G_10G_10G_Q: - case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: - case TLV_PORT_MODE_10G_10G_10G_10G_Q2: + case TLV_PORT_MODE_4x1_NA: /* mode 4 */ + case TLV_PORT_MODE_2x1_2x1: /* mode 5 */ + case TLV_PORT_MODE_NA_4x1: /* mode 8 */ bandwidth = 10000 * 4; break; - case TLV_PORT_MODE_40G: + /* Legacy Medford-only mode. Do not use (see bug63270) */ + case TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2: /* mode 9 */ + bandwidth = 10000 * 4; + break; + case TLV_PORT_MODE_1x4_NA: /* mode 1 */ bandwidth = 40000; break; - case TLV_PORT_MODE_40G_40G: + case TLV_PORT_MODE_1x4_1x4: /* mode 3 */ bandwidth = 40000 * 2; break; - case TLV_PORT_MODE_40G_10G_10G: - case TLV_PORT_MODE_10G_10G_40G: + case TLV_PORT_MODE_1x4_2x1: /* mode 6 */ + case TLV_PORT_MODE_2x1_1x4: /* mode 7 */ bandwidth = 40000 + (10000 * 2); break; default: @@ -1468,8 +1471,8 @@ static struct ef10_external_port_map_s { */ { EFX_FAMILY_MEDFORD, - (1U << TLV_PORT_MODE_10G) | /* mode 0 */ - (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */ + (1U << TLV_PORT_MODE_1x1_NA) | /* mode 0 */ + (1U << TLV_PORT_MODE_1x1_1x1), /* mode 2 */ 1, /* ports per cage */ 1 /* first cage */ }, @@ -1483,10 +1486,10 @@ static struct ef10_external_port_map_s { */ { EFX_FAMILY_MEDFORD, - (1U << TLV_PORT_MODE_40G) | /* mode 1 */ - (1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */ - (1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */ - (1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */ + (1U << TLV_PORT_MODE_1x4_NA) | /* mode 1 */ + (1U << TLV_PORT_MODE_1x4_1x4) | /* mode 3 */ + (1U << TLV_PORT_MODE_1x4_2x1) | /* mode 6 */ + (1U << TLV_PORT_MODE_2x1_1x4) | /* mode 7 */ /* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */ (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */ 2, /* ports per cage */ @@ -1502,9 +1505,9 @@ static struct ef10_external_port_map_s { */ { EFX_FAMILY_MEDFORD, - (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */ + (1U << TLV_PORT_MODE_2x1_2x1) | /* mode 5 */ /* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */ - (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */ + (1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */ 4, /* ports per cage */ 1 /* first cage */ }, @@ -1518,7 +1521,7 @@ static struct ef10_external_port_map_s { */ { EFX_FAMILY_MEDFORD, - (1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */ + (1U << TLV_PORT_MODE_NA_4x1), /* mode 8 */ 4, /* ports per cage */ 2 /* first cage */ },