From patchwork Thu Jul 26 13:38:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Dumitrescu X-Patchwork-Id: 43405 X-Patchwork-Delegate: cristian.dumitrescu@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E8BB52BE2; Thu, 26 Jul 2018 15:38:16 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id D92DA1C01 for ; Thu, 26 Jul 2018 15:38:14 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2018 06:38:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,405,1526367600"; d="scan'208";a="70113714" Received: from silpixa00382658.ir.intel.com ([10.237.223.29]) by orsmga003.jf.intel.com with ESMTP; 26 Jul 2018 06:38:11 -0700 From: Cristian Dumitrescu To: dev@dpdk.org Date: Thu, 26 Jul 2018 14:38:04 +0100 Message-Id: <1532612284-239798-1-git-send-email-cristian.dumitrescu@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [dpdk-dev] [PATCH] examples/ip_pipeline: add example script for rss X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add example script to demonstrate Receive Side Scaling (RSS). Signed-off-by: Cristian Dumitrescu --- examples/ip_pipeline/examples/rss.cli | 112 ++++++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) create mode 100644 examples/ip_pipeline/examples/rss.cli diff --git a/examples/ip_pipeline/examples/rss.cli b/examples/ip_pipeline/examples/rss.cli new file mode 100644 index 0000000..1ff4bf1 --- /dev/null +++ b/examples/ip_pipeline/examples/rss.cli @@ -0,0 +1,112 @@ +; SPDX-License-Identifier: BSD-3-Clause +; Copyright(c) 2010-2018 Intel Corporation + +; This setup demonstrates the usage of NIC Receive Side Scaling (RSS) feature. +; Each NIC splits the input traffic into 4 RX queues, with each of its RX queues +; being handled by a different pipeline: +; +; +-----------+ +----------+ +; +--------------------------->| | | | +; | +------------------->| PIPELINE0 +--->| LINK 0 |---> +; | | +------------->| (CORE A) | | TX | +; | | | +------->| | | | +; | | | | +-----------+ +----------+ +; +----------+ | | | | +; | |-------+ | | | +;--->| LINK 0 |-----------+ | | | +; | RX |---------+ | | | | +; | |-------+ | | | | | +; +----------+ | | | | | | +-----------+ +----------+ +; | | +---|-----|-----|------->| | | | +; +----------+ | | | +---|-----|------->| PIPELINE1 +--->| LINK 1 |---> +; | |-------|-|-----+ | | +---|------->| (CORE B) | | TX | +;--->| LINK 1 |-------|-|-------+ | | | +----->| | | | +; | RX |-------|-|-------+ | | | | +-----------+ +----------+ +; | |-------|-|-----+ | | | | | +; +----------+ | | | | | | | | +; | | | | | | | | +; +----------+ | | | | | | | | +; | |-------|-|-----|-|---+ | | | +;--->| LINK 2 |-------|-|-----|-|-----+ | | +-----------+ +----------+ +; | RX |-----+ | +-----|-|---------|-|----->| | | | +; | |---+ | | | +---------|-|----->| PIPELINE2 +--->| LINK 2 |---> +; +----------+ | +-|-------|-----------|-|----->| (CORE C) | | TX | +; | | | | | +--->| | | | +; +----------+ | | | | | | +-----------+ +----------+ +; | |---|---|-------|-----------+ | | +;--->| LINK 3 |---|---|-------|-------------+ | +; | RX |---|---|-------|---------------+ +; | |---|---|-------|-----------+ +; +----------+ | | | | +; | | | | +-----------+ +----------+ +; | +-------|-----------|------->| | | | +; | +-----------|------->| PIPELINE3 +--->| LINK 3 |---> +; +-----------------------|------->| (CORE D) | | TX | +; +------->| | | | +; +-----------+ +----------+ +; +; + +mempool MEMPOOL0 buffer 2304 pool 32K cache 256 cpu 0 + +link LINK0 dev 0000:02:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 +link LINK1 dev 0000:02:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 +link LINK2 dev 0000:06:00.0 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 +link LINK3 dev 0000:06:00.1 rxq 4 128 MEMPOOL0 txq 1 512 promiscuous on rss 0 1 2 3 + +pipeline PIPELINE0 period 10 offset_port_id 0 cpu 0 +pipeline PIPELINE0 port in bsz 32 link LINK0 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK1 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK2 rxq 0 +pipeline PIPELINE0 port in bsz 32 link LINK3 rxq 0 +pipeline PIPELINE0 port out bsz 32 link LINK0 txq 0 +pipeline PIPELINE0 table match stub +pipeline PIPELINE0 port in 0 table 0 +pipeline PIPELINE0 port in 1 table 0 +pipeline PIPELINE0 port in 2 table 0 +pipeline PIPELINE0 port in 3 table 0 +pipeline PIPELINE0 table 0 rule add match default action fwd port 0 + +pipeline PIPELINE1 period 10 offset_port_id 0 cpu 0 +pipeline PIPELINE1 port in bsz 32 link LINK0 rxq 1 +pipeline PIPELINE1 port in bsz 32 link LINK1 rxq 1 +pipeline PIPELINE1 port in bsz 32 link LINK2 rxq 1 +pipeline PIPELINE1 port in bsz 32 link LINK3 rxq 1 +pipeline PIPELINE1 port out bsz 32 link LINK1 txq 0 +pipeline PIPELINE1 table match stub +pipeline PIPELINE1 port in 0 table 0 +pipeline PIPELINE1 port in 1 table 0 +pipeline PIPELINE1 port in 2 table 0 +pipeline PIPELINE1 port in 3 table 0 +pipeline PIPELINE1 table 0 rule add match default action fwd port 0 + +pipeline PIPELINE2 period 10 offset_port_id 0 cpu 0 +pipeline PIPELINE2 port in bsz 32 link LINK0 rxq 2 +pipeline PIPELINE2 port in bsz 32 link LINK1 rxq 2 +pipeline PIPELINE2 port in bsz 32 link LINK2 rxq 2 +pipeline PIPELINE2 port in bsz 32 link LINK3 rxq 2 +pipeline PIPELINE2 port out bsz 32 link LINK2 txq 0 +pipeline PIPELINE2 table match stub +pipeline PIPELINE2 port in 0 table 0 +pipeline PIPELINE2 port in 1 table 0 +pipeline PIPELINE2 port in 2 table 0 +pipeline PIPELINE2 port in 3 table 0 +pipeline PIPELINE2 table 0 rule add match default action fwd port 0 + +pipeline PIPELINE3 period 10 offset_port_id 0 cpu 0 +pipeline PIPELINE3 port in bsz 32 link LINK0 rxq 3 +pipeline PIPELINE3 port in bsz 32 link LINK1 rxq 3 +pipeline PIPELINE3 port in bsz 32 link LINK2 rxq 3 +pipeline PIPELINE3 port in bsz 32 link LINK3 rxq 3 +pipeline PIPELINE3 port out bsz 32 link LINK3 txq 0 +pipeline PIPELINE3 table match stub +pipeline PIPELINE3 port in 0 table 0 +pipeline PIPELINE3 port in 1 table 0 +pipeline PIPELINE3 port in 2 table 0 +pipeline PIPELINE3 port in 3 table 0 +pipeline PIPELINE3 table 0 rule add match default action fwd port 0 + +thread 1 pipeline PIPELINE0 enable +thread 2 pipeline PIPELINE1 enable +thread 3 pipeline PIPELINE2 enable +thread 4 pipeline PIPELINE3 enable