From patchwork Sat Apr 28 03:03:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tonghao Zhang X-Patchwork-Id: 39158 X-Patchwork-Delegate: helin.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 134D17CAA; Sat, 28 Apr 2018 05:04:09 +0200 (CEST) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by dpdk.org (Postfix) with ESMTP id 7A3136CD8 for ; Sat, 28 Apr 2018 05:04:02 +0200 (CEST) Received: by mail-pg0-f65.google.com with SMTP id b9-v6so2811481pgf.6 for ; Fri, 27 Apr 2018 20:04:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EGGjhfzGP7pWSC5b7+hL0+fFxwdRPbayTMY2G83XTF0=; b=ZArSGhL/Mp18Zl0bGKjo9HTGOOxKC6h5euv9iPOWl1RfjxwWUPidOtqk2EQrHDEz1c D2EG7xis8klGYsW2qpcG2cKZ8TRwBN31+bRPK6BZenznUr8zIoOogemCZi2e83UtS949 0OI+HKeh3ELin9ifOWi0AEVSYH3PJP4hORyqwRmhjOYvo8DcuWI5nTPeokWUJcHcWCZa ccNUScgqWVTwVpAas+DxnYoTxoftXwFKCDnL78ZZmwfJADus/ShJZMOJ/BmL/4hxG3R5 nsO3Qyttm0w1zAdfWbA+7yTgSc24WPr+izPJhumk4pLgOTfVPOMaZanxXXEZT4e6OEEv RS9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EGGjhfzGP7pWSC5b7+hL0+fFxwdRPbayTMY2G83XTF0=; b=oKWgq0/3Qg47ZtXf6V+jtsDIxIR4Ov7FF/w4w5/DcvdtSMHU4JeBSWwn+tSeTdzxjL jUw6n7okHZCTy5ETLo141abaXwVtkHB0WuXHSOSmYvm9NWiCCQwy16OEYRDmCXzRVKbe ho1YEhuneiZagleRbVe/K9oR3xGdEeEcGeD/rJzoN4lLclMVtFu1rSi5saC0+hFpx6O3 W26pbCG+Rt299RiAmapPqEfOCtjiIv6OGBZw75YhP4UTG65yO6qqzXcf3vkMmpT9GIAY hdPEwGlLkMkp7XERDWQC5GLrZ+HxxNdtYx4ykpohEsPm9wS28BFbZvcDgzxejn5Pithm 8Vdw== X-Gm-Message-State: ALQs6tDZA2Wis2iEULKrcaQ/AdOM3TYpqvYrNshRisGAkGa3vAn2RXKB rlJb8mv9SG7heEHSY9jO11E= X-Google-Smtp-Source: AB8JxZoG1ibmCdh28nxEBmhByzMZiLbD5DIVGrEeGidXsQQJIeUmUhKseajxv2HkmRN0TGGjoqkwjQ== X-Received: by 2002:a17:902:1007:: with SMTP id b7-v6mr4487531pla.205.1524884641662; Fri, 27 Apr 2018 20:04:01 -0700 (PDT) Received: from local.opencloud.tech.localdomain ([13.94.31.177]) by smtp.gmail.com with ESMTPSA id n17-v6sm4634416pgd.58.2018.04.27.20.03.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Apr 2018 20:04:01 -0700 (PDT) From: xiangxia.m.yue@gmail.com To: qi.z.zhang@intel.com, ferruh.yigit@intel.com, helin.zhang@intel.com, beilei.xing@intel.com, wei.dai@intel.com Cc: dev@dpdk.org, Tonghao Zhang Date: Fri, 27 Apr 2018 20:03:40 -0700 Message-Id: <1524884620-64598-5-git-send-email-xiangxia.m.yue@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1524884620-64598-1-git-send-email-xiangxia.m.yue@gmail.com> References: <1524884620-64598-1-git-send-email-xiangxia.m.yue@gmail.com> Subject: [dpdk-dev] [PATCH net-next v4 4/4] net/ixgbevf: save IXGBE_VTEIMS to intr->mask for performance. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tonghao Zhang If dpdk APPs call the rte_eth_dev_rx_intr_enable or rte_eth_dev_rx_intr_disable frequently, and ixgbe vf will read the IXGBE_VTEIMS register everytime. The patch saves the IXGBE_VTEIMS to mask to avoid read frequently. Signed-off-by: Tonghao Zhang Acked-by: Beilei Xing Acked-by: Wei Dai --- drivers/net/ixgbe/ixgbe_ethdev.c | 55 +++++++++++++++++++++++++--------------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 07b4c1b..95c4d28 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -237,8 +237,8 @@ static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, static void ixgbevf_dev_stop(struct rte_eth_dev *dev); static void ixgbevf_dev_close(struct rte_eth_dev *dev); static int ixgbevf_dev_reset(struct rte_eth_dev *dev); -static void ixgbevf_intr_disable(struct ixgbe_hw *hw); -static void ixgbevf_intr_enable(struct ixgbe_hw *hw); +static void ixgbevf_intr_disable(struct rte_eth_dev *dev); +static void ixgbevf_intr_enable(struct rte_eth_dev *dev); static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); @@ -1603,7 +1603,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) ixgbevf_dev_stats_reset(eth_dev); /* Disable the interrupts for VF */ - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(eth_dev); hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ diag = hw->mac.ops.reset_hw(hw); @@ -1672,7 +1672,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) rte_intr_callback_register(intr_handle, ixgbevf_dev_interrupt_handler, eth_dev); rte_intr_enable(intr_handle); - ixgbevf_intr_enable(hw); + ixgbevf_intr_enable(eth_dev); PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", eth_dev->data->port_id, pci_dev->id.vendor_id, @@ -1705,7 +1705,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) eth_dev->tx_pkt_burst = NULL; /* Disable the interrupts for VF */ - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(eth_dev); rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; @@ -4933,19 +4933,32 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, * Virtual Function operations */ static void -ixgbevf_intr_disable(struct ixgbe_hw *hw) +ixgbevf_intr_disable(struct rte_eth_dev *dev) { + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct ixgbe_hw *hw = + IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + PMD_INIT_FUNC_TRACE(); /* Clear interrupt mask to stop from interrupts being generated */ IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); IXGBE_WRITE_FLUSH(hw); + + /* Clear mask value. */ + intr->mask = 0; } static void -ixgbevf_intr_enable(struct ixgbe_hw *hw) +ixgbevf_intr_enable(struct rte_eth_dev *dev) { + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct ixgbe_hw *hw = + IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + PMD_INIT_FUNC_TRACE(); /* VF enable interrupt autoclean */ @@ -4954,6 +4967,9 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); IXGBE_WRITE_FLUSH(hw); + + /* Save IXGBE_VTEIMS value to mask. */ + intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; } static int @@ -5096,7 +5112,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, rte_intr_enable(intr_handle); /* Re-enable interrupt for VF */ - ixgbevf_intr_enable(hw); + ixgbevf_intr_enable(dev); return 0; } @@ -5110,7 +5126,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, PMD_INIT_FUNC_TRACE(); - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(dev); hw->adapter_stopped = 1; ixgbe_stop_adapter(hw); @@ -5602,17 +5618,17 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; - uint32_t mask; + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t vec = IXGBE_MISC_VEC_ID; - mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS); if (rte_intr_allow_others(intr_handle)) vec = IXGBE_RX_VEC_START; - mask |= (1 << vec); + intr->mask |= (1 << vec); RTE_SET_USED(queue_id); - IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); + IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); rte_intr_enable(intr_handle); @@ -5622,19 +5638,19 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) { - uint32_t mask; + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; uint32_t vec = IXGBE_MISC_VEC_ID; - mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS); if (rte_intr_allow_others(intr_handle)) vec = IXGBE_RX_VEC_START; - mask &= ~(1 << vec); + intr->mask &= ~(1 << vec); RTE_SET_USED(queue_id); - IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); + IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); return 0; } @@ -8273,7 +8289,7 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev) struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ixgbe_interrupt *intr = IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(dev); /* read-on-clear nic registers here */ eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); @@ -8290,7 +8306,6 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev) static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) { - struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ixgbe_interrupt *intr = IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); @@ -8299,7 +8314,7 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev) intr->flags &= ~IXGBE_FLAG_MAILBOX; } - ixgbevf_intr_enable(hw); + ixgbevf_intr_enable(dev); return 0; }