[dpdk-dev,64/80] net/sfc/base: group Medford external port mapping entries
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Commit Message
From: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_nic.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
@@ -1352,21 +1352,6 @@ static struct ef10_external_port_map_s {
1 /* first cage */
},
/*
- * Modes that on Medford allocate each port number to a separate
- * cage.
- * port 0 -> cage 1
- * port 1 -> cage 2
- * port 2 -> cage 3
- * port 3 -> cage 4
- */
- {
- EFX_FAMILY_MEDFORD,
- (1U << TLV_PORT_MODE_10G) | /* mode 0 */
- (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
- 1, /* ports per cage */
- 1 /* first cage */
- },
- /*
* Modes which for Huntington identify a chip variant where 2
* adjacent port numbers map to each cage.
* SFN7x42Q (Monza):
@@ -1385,6 +1370,21 @@ static struct ef10_external_port_map_s {
1 /* first cage */
},
/*
+ * Modes that on Medford allocate each port number to a separate
+ * cage.
+ * port 0 -> cage 1
+ * port 1 -> cage 2
+ * port 2 -> cage 3
+ * port 3 -> cage 4
+ */
+ {
+ EFX_FAMILY_MEDFORD,
+ (1U << TLV_PORT_MODE_10G) | /* mode 0 */
+ (1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
+ 1, /* ports per cage */
+ 1 /* first cage */
+ },
+ /*
* Modes that on Medford allocate 2 adjacent port numbers to each
* cage.
* port 0 -> cage 1