From patchwork Fri Jan 12 06:45:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Rosen" X-Patchwork-Id: 33641 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2BA85325F; Fri, 12 Jan 2018 07:47:41 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id C5A051041; Fri, 12 Jan 2018 07:47:39 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Jan 2018 22:47:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,348,1511856000"; d="scan'208";a="166171144" Received: from dpdkx8602.sh.intel.com ([10.67.110.200]) by orsmga004.jf.intel.com with ESMTP; 11 Jan 2018 22:47:37 -0800 From: Rosen Xu To: dev@dpdk.org Cc: stable@dpdk.org Date: Fri, 12 Jan 2018 14:45:25 +0800 Message-Id: <1515739525-62646-1-git-send-email-rosen.xu@intel.com> X-Mailer: git-send-email 1.8.3.1 Subject: [dpdk-dev] [PATCH] net/i40e: fix issue of pctype does't take effert in X722 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fixes: a286ebeb0714 ("net/i40e: add dynamic mapping of SW flow types to HW pctypes") Cc: stable@dpdk.org Signed-off-by: Rosen Xu --- drivers/net/i40e/i40e_ethdev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index d80671a..8686ca5 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -1057,7 +1057,6 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) return 0; } i40e_set_default_ptype_table(dev); - i40e_set_default_pctype_table(dev); pci_dev = RTE_ETH_DEV_TO_PCI(dev); intr_handle = &pci_dev->intr_handle; @@ -1103,6 +1102,8 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw) return ret; } + i40e_set_default_pctype_table(dev); + /* * To work around the NVM issue, initialize registers * for packet type of QinQ by software.