From patchwork Thu Jan 11 16:39:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tonghao Zhang X-Patchwork-Id: 33603 X-Patchwork-Delegate: helin.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 64083A48B; Thu, 11 Jan 2018 17:40:04 +0100 (CET) Received: from mail-pg0-f66.google.com (mail-pg0-f66.google.com [74.125.83.66]) by dpdk.org (Postfix) with ESMTP id 69006A489 for ; Thu, 11 Jan 2018 17:40:03 +0100 (CET) Received: by mail-pg0-f66.google.com with SMTP id z17so2525299pgc.4 for ; Thu, 11 Jan 2018 08:40:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kYcjXDxg059Q8BGQ47JUKmZjDcCxGFn/aoBXZmgzwdA=; b=DhUx9NNC0Jeb6/7N/xUYAJVt+s6cWDSgvIq8ng05i6CdT0iKbBjTsDRw99dsq3bQOy YjlrXT2UZg68LM5bcFjjtG0E0Si+pMCK71oKyvHprylp/F87oPMx+OhO4n8cl4h0g4+U +6M+pWP9rvjYwI8KIfQm+HPUAAmV9onxiGAJnwgmFtQta1jJAm6vHL1fNdj9IvNSySfC 99PkcM9GXjEqV1Pc83rZiY083tpna9cHVQxG04Y20RXKKrVDql0ssL7ALtkYqWdEsSF5 GWg6V8n4oXgDgS+LspIapHLyNuycLFemKkRwq7BqOh+F+wIm8Q4e9Gdbyym3Q8FGTF5v Jf3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kYcjXDxg059Q8BGQ47JUKmZjDcCxGFn/aoBXZmgzwdA=; b=aEo2E+sOaGdr2VQfwReSMUE6I/HohQRY0pmgmIIJ2J74KLgLRsSnuFQP2YUAvHfsxJ mVMHQhsRaDIF+E/QJt2ix03E+OH1RFoyx5wdwQf0SmdDg3iO5kV8S7Y8h5EW4v0hcTzp TITiPmySGelTBVK812IeDYblwcDKGUrSqVVoCO14tpGjMSsklGvasZfmOG9dFbhv9sY+ lNpPbA5TxeDTSodhMqL1mT/MQMu3qyCwyBQOr3S6PXOXXWcMczMnlObvvK92HhHZ+h3Y KZqqXAXnb2jY8Y/oGvZTDiiaKw+6m7CRIoikkn3IbU86EQVWL6o3cKKE3dRVx1LDiEaY pdPQ== X-Gm-Message-State: AKGB3mIIH9Z4qd3l6hkSOuOSEY/wWav2dkhMqUg7OCeKw+SlNmai1qCG FwuDpjD4AXM3zWf6kPjVI5xDlPFh X-Google-Smtp-Source: ACJfBovWs3tYs1iBsQhdR6D4Pm9G8yBh9Mks1Soo5PrPbM7ToCHVeu3UNkV8rHrt6GKRwmcRGk+W6g== X-Received: by 10.99.110.71 with SMTP id j68mr18038985pgc.54.1515688802677; Thu, 11 Jan 2018 08:40:02 -0800 (PST) Received: from local.opencloud.tech.localdomain ([183.240.196.57]) by smtp.gmail.com with ESMTPSA id w21sm40940126pfl.50.2018.01.11.08.40.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Jan 2018 08:40:02 -0800 (PST) From: xiangxia.m.yue@gmail.com To: beilei.xing@intel.com, dev@dpdk.org Cc: Tonghao Zhang Date: Thu, 11 Jan 2018 08:39:50 -0800 Message-Id: <1515688791-2794-3-git-send-email-xiangxia.m.yue@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1515688791-2794-1-git-send-email-xiangxia.m.yue@gmail.com> References: <1515688791-2794-1-git-send-email-xiangxia.m.yue@gmail.com> Subject: [dpdk-dev] [PATCH v2 3/4] net/ixgbevf: save IXGBE_VTEIMS to intr->mask for performance. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tonghao Zhang If dpdk APPs call the rte_eth_dev_rx_intr_enable or rte_eth_dev_rx_intr_disable frequently, and ixgbe vf will read the IXGBE_VTEIMS register everytime. The patch saves the IXGBE_VTEIMS to mask to avoid read frequently. Signed-off-by: Tonghao Zhang Acked-by: Beilei Xing Acked-by: Wei Dai --- drivers/net/ixgbe/ixgbe_ethdev.c | 55 +++++++++++++++++++++++++--------------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 49f486a..cab243d 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -270,8 +270,8 @@ static int ixgbevf_dev_link_update(struct rte_eth_dev *dev, static void ixgbevf_dev_stop(struct rte_eth_dev *dev); static void ixgbevf_dev_close(struct rte_eth_dev *dev); static int ixgbevf_dev_reset(struct rte_eth_dev *dev); -static void ixgbevf_intr_disable(struct ixgbe_hw *hw); -static void ixgbevf_intr_enable(struct ixgbe_hw *hw); +static void ixgbevf_intr_disable(struct rte_eth_dev *dev); +static void ixgbevf_intr_enable(struct rte_eth_dev *dev); static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev); @@ -1665,7 +1665,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) ixgbevf_dev_stats_reset(eth_dev); /* Disable the interrupts for VF */ - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(eth_dev); hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */ diag = hw->mac.ops.reset_hw(hw); @@ -1734,7 +1734,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) rte_intr_callback_register(intr_handle, ixgbevf_dev_interrupt_handler, eth_dev); rte_intr_enable(intr_handle); - ixgbevf_intr_enable(hw); + ixgbevf_intr_enable(eth_dev); PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s", eth_dev->data->port_id, pci_dev->id.vendor_id, @@ -1767,7 +1767,7 @@ static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev) eth_dev->tx_pkt_burst = NULL; /* Disable the interrupts for VF */ - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(eth_dev); rte_free(eth_dev->data->mac_addrs); eth_dev->data->mac_addrs = NULL; @@ -4953,19 +4953,32 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, * Virtual Function operations */ static void -ixgbevf_intr_disable(struct ixgbe_hw *hw) +ixgbevf_intr_disable(struct rte_eth_dev *dev) { + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct ixgbe_hw *hw = + IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + PMD_INIT_FUNC_TRACE(); /* Clear interrupt mask to stop from interrupts being generated */ IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK); IXGBE_WRITE_FLUSH(hw); + + /* Clear mask value. */ + intr->mask = 0; } static void -ixgbevf_intr_enable(struct ixgbe_hw *hw) +ixgbevf_intr_enable(struct rte_eth_dev *dev) { + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); + struct ixgbe_hw *hw = + IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + PMD_INIT_FUNC_TRACE(); /* VF enable interrupt autoclean */ @@ -4974,6 +4987,9 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK); IXGBE_WRITE_FLUSH(hw); + + /* Save IXGBE_VTEIMS value to mask. */ + intr->mask = IXGBE_VF_IRQ_ENABLE_MASK; } static int @@ -5099,7 +5115,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, rte_intr_enable(intr_handle); /* Re-enable interrupt for VF */ - ixgbevf_intr_enable(hw); + ixgbevf_intr_enable(dev); return 0; } @@ -5113,7 +5129,7 @@ static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, PMD_INIT_FUNC_TRACE(); - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(dev); hw->adapter_stopped = 1; ixgbe_stop_adapter(hw); @@ -5611,17 +5627,17 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) { struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; - uint32_t mask; + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); uint32_t vec = IXGBE_MISC_VEC_ID; - mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS); if (rte_intr_allow_others(intr_handle)) vec = IXGBE_RX_VEC_START; - mask |= (1 << vec); + intr->mask |= (1 << vec); RTE_SET_USED(queue_id); - IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); + IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); rte_intr_enable(intr_handle); @@ -5631,19 +5647,19 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) { - uint32_t mask; + struct ixgbe_interrupt *intr = + IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; uint32_t vec = IXGBE_MISC_VEC_ID; - mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS); if (rte_intr_allow_others(intr_handle)) vec = IXGBE_RX_VEC_START; - mask &= ~(1 << vec); + intr->mask &= ~(1 << vec); RTE_SET_USED(queue_id); - IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask); + IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); return 0; } @@ -8200,7 +8216,7 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev) struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ixgbe_interrupt *intr = IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); - ixgbevf_intr_disable(hw); + ixgbevf_intr_disable(dev); /* read-on-clear nic registers here */ eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR); @@ -8217,7 +8233,6 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev) static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev) { - struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); struct ixgbe_interrupt *intr = IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); @@ -8226,7 +8241,7 @@ static void ixgbevf_mbx_process(struct rte_eth_dev *dev) intr->flags &= ~IXGBE_FLAG_MAILBOX; } - ixgbevf_intr_enable(hw); + ixgbevf_intr_enable(dev); return 0; }