From patchwork Thu Oct 26 13:44:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tonghao Zhang X-Patchwork-Id: 30973 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B529B1BB0C; Thu, 26 Oct 2017 15:45:12 +0200 (CEST) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by dpdk.org (Postfix) with ESMTP id 7696B1BB0C for ; Thu, 26 Oct 2017 15:45:09 +0200 (CEST) Received: by mail-pf0-f196.google.com with SMTP id t188so2541934pfd.10 for ; Thu, 26 Oct 2017 06:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aBlNU1rBoqdLtKXZPMD3skt9TDA/sDo2dzl5c7KdHb4=; b=iffTpF/VTnXRDZpNe8S3xUsqm3ePq4LcmD3ErghLiiNS0rKMTltfmagsyW8bNMqmgh EFGDUWGQhS1ElVNmy9bDDvW4WYUg8S2SXKFA3F5f5Jnt50qZq9YK90Zk88yNZjLCpmC3 0bal+iw0QRIOj4iGnf9jCAWnABpjqFMfWalvpbN+NpZVEMozll7Mscd+plu0tZyqI5mg NQy48ASeFGZ7AxqIFYhr4Qc61Y1NcAFI+h3no9EuwO3R4lhJnX2mk0T3j5fT+J166Tqc MZiY+b3k7c0d9Nz+jJb+aA2cxH0rcsMCu80x+9p7IdTy1uX8z6Odzt6kow+txwkUE09A OvxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aBlNU1rBoqdLtKXZPMD3skt9TDA/sDo2dzl5c7KdHb4=; b=J0bb0EYIsUOMiprx7vMUc+X5mTgLOY/hUXJEbscNjr2aXCh229aShFkr6BjDTeZAd4 iRMMAlxLBKDGX93pQZpeiXRgWFrV4wJPMVSPzWFEEAr9ITzI5P5I9Cs5XxrW8copMGI/ uqyxO4ZcnYN0LoT2dfQwRWaLpxkhR/9K8Lim3xLJhybcoxQIqjBGIQ1RQDwr4l+G9kNJ yJptOSyga1UjmHM9QMoAuDFvcT+scT+si/ssc2U6aH6WPqbqkEExbPYMueoZt2ToFo21 25uXE7Qsv+3pSRZAHom+Yb1SqiSDYSZ/8G01CPQOl/T7pmP3BiRKAob9AieWG7mIgnTn x+Rw== X-Gm-Message-State: AMCzsaWBKf6zk3/CZpvndtuYSXJKKbYHEwJEsv+TUtOBBz0nSIomAt8B iQZr8+pqTmRPE5Bpt0km16TzAw== X-Google-Smtp-Source: ABhQp+SgbFZQPRa1l5J5hmlYGfGFn4wJQnlQSv3D+5oPDiLCUMxphy1O4RCRwWUfLZQIwvwXR3p8zA== X-Received: by 10.84.131.34 with SMTP id 31mr4446918pld.449.1509025508633; Thu, 26 Oct 2017 06:45:08 -0700 (PDT) Received: from local.opencloud.tech.localdomain ([13.94.31.177]) by smtp.gmail.com with ESMTPSA id w9sm10921172pfk.16.2017.10.26.06.45.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Oct 2017 06:45:08 -0700 (PDT) From: xiangxia.m.yue@gmail.com To: dev@dpdk.org Cc: Tonghao Zhang , Tonghao Zhang Date: Thu, 26 Oct 2017 06:44:44 -0700 Message-Id: <1509025484-15771-4-git-send-email-xiangxia.m.yue@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1509025484-15771-1-git-send-email-xiangxia.m.yue@gmail.com> References: <1509025484-15771-1-git-send-email-xiangxia.m.yue@gmail.com> Subject: [dpdk-dev] [PATCH 4/4] net/ixgbevf: add check for rte_intr_enable. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tonghao Zhang When we bind the ixgbevf to vfio and call the rte_eth_dev_rx_intr_enable and rte_eth_dev_rx_intr_disable frequently, the interrupt setting (msi_set_mask_bit) will take more CPU as show below. rte_intr_enable call the ioctl to map the fd to interrupts frequently. perf top: 5.45% [kernel] [k] msi_set_mask_bit It is unnecessary to call the rte_intr_enable in ixgbe_dev_rx_queue_intr_enable. because the fds has been mapped to interrupt and not unmapped in ixgbe_dev_rx_queue_intr_disable. This patch add checks for using VFIO. With the patch, msi_set_mask_bit is not listed in perl any more. Any suggestion will be welcome. Signed-off-by: Tonghao Zhang Signed-off-by: Tonghao Zhang --- drivers/net/ixgbe/ixgbe_ethdev.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index f534f20..b958734 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -5631,7 +5631,9 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) RTE_SET_USED(queue_id); IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask); - rte_intr_enable(intr_handle); + if (intr_handle->type == RTE_INTR_HANDLE_UIO || + intr_handle->type == RTE_INTR_HANDLE_UIO_INTX) + rte_intr_enable(intr_handle); return 0; } @@ -5680,7 +5682,10 @@ static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on) mask &= (1 << (queue_id - 32)); IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); } - rte_intr_enable(intr_handle); + + if (intr_handle->type == RTE_INTR_HANDLE_UIO || + intr_handle->type == RTE_INTR_HANDLE_UIO_INTX) + rte_intr_enable(intr_handle); return 0; }