From patchwork Thu Mar 2 11:32:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shijith Thotton X-Patchwork-Id: 21093 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id BB7B1FA48; Thu, 2 Mar 2017 12:39:01 +0100 (CET) Received: from NAM03-CO1-obe.outbound.protection.outlook.com (mail-co1nam03on0070.outbound.protection.outlook.com [104.47.40.70]) by dpdk.org (Postfix) with ESMTP id 894BFF962 for ; Thu, 2 Mar 2017 12:38:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=GzDCU/6wpR5ZOpfLHdyDAmN2em2BJA5lYoX9grTY+Zg=; b=ft1ctItisnEPo1+cQtiVi3nmfsDDbRwghKNN9EYze1RVUo1pk+osbCxjUGh4/SFyZkpPCkkjDq1SLSyfEgxQK+WqCvAx300h8fN8iRIM+I7hantMXV7Qbr91rY2z7iYBVVqKtmhum9gB4O7y0CCpWyu1dwnh9PIhZMs15mEuutk= Authentication-Results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=caviumnetworks.com; Received: from lio357.in.caveonetworks.com (14.140.2.178) by CY1PR07MB2277.namprd07.prod.outlook.com (10.164.112.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.947.12; Thu, 2 Mar 2017 11:38:55 +0000 From: Shijith Thotton To: ferruh.yigit@intel.com Cc: dev@dpdk.org, Jerin Jacob , Derek Chickles , Venkat Koppula , Srisivasubramanian S , Mallesham Jatharakonda Date: Thu, 2 Mar 2017 17:02:25 +0530 Message-Id: <1488454371-3342-21-git-send-email-shijith.thotton@caviumnetworks.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488454371-3342-1-git-send-email-shijith.thotton@caviumnetworks.com> References: <1487669225-30091-1-git-send-email-shijith.thotton@caviumnetworks.com> <1488454371-3342-1-git-send-email-shijith.thotton@caviumnetworks.com> MIME-Version: 1.0 X-Originating-IP: [14.140.2.178] X-ClientProxiedBy: BM1PR01CA0021.INDPRD01.PROD.OUTLOOK.COM (10.163.198.156) To CY1PR07MB2277.namprd07.prod.outlook.com (10.164.112.155) X-MS-Office365-Filtering-Correlation-Id: 3c21c4c6-4f8d-4433-0d7c-08d46160b705 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:CY1PR07MB2277; X-Microsoft-Exchange-Diagnostics: 1; CY1PR07MB2277; 3:95y8FUOPti7Ke+oCKYZMO4tCHkRu/IpzWCDsxw7qnqUq3Ah/Jj2XVKfCd5JBmBor1z51wNEa7xtuFxXCf5vZNQf4xSiijwtwh/KdykNehTwxnMVviogtoVSbf7ltTjUZe78YJ8SxcVkBEJEmMPGUTowhX+FdSa8bs6nx4QrnSueG20Ml/Osijr50TVapfQptj7VwTSrlf1IbVKXUzhUmndIfTgdx76m6RK1DvneR/wMRJfvmE81GGan+FUzVKCZLX2mSgDjaaKR/nLG4ob0RRA==; 25:ulZm2M96n9iYNCPsgzB9LieWU1sA29MI4mUzlkdkhE9WlebYNxlprWGJvyiRnqxNA9gQuB0Z6D3bfZ3K5MECEmlR1XgRWMmP4MYO/UGNpJ0K8C/7sQa8rfbJiI1W+NYJ8MU6zhzAe8sfrWJwSZTurFRw2M6GomPdDT6JOfsGPGTRhomhGzCcIOTmrLk0nRebg2kheZB41myXtFcovFRodlr2PyDLh3kwEflpFuUSwQuLKqsFMWPcYIOQstF+uLcJY952+KY/EuoklQWsTf/jv0CVNJXA1tfrM5d+WFAyT9AgFGDwuXApMqD6bJ4zx6SGEfPyKMLZVwT1le+q8zcCAvuODIna8t5cnEhVRILp3sVQj+11HlDZkUpBc6E1m1roJtyUVv6JPUXw/65GjXtRlXoZsiSd2CAgIkOp5+l3VCg5EA8/TL5qUYaPJryQc63jBGwMgUspddiXLyXsoCztyw== X-Microsoft-Exchange-Diagnostics: 1; CY1PR07MB2277; 31:e2hN/eduSbIUBeav93o+6IZwin1+A+niqnzMsKhrodDjImcDtRJF9hkZTE6ME+m339QR1jzCUfM1EMWXNghiqqzDFizfmmcoZl4qJ/175sIeIIhmcu0X52azZkW1PjgZzPAD2R4jmzkzg0Fo2YtH/sVfqL9tZDsu7gLRagkjpFhu5J4cjg+il0IlhBurRP69/BPYV9dVovVEVY1VHGmrTXgMAm0XTfQD87hqkKlhJE8=; 20:Hh8tNiwLUdQPdRjb4jWSeXHbbvmer6y6XWrCNaUzK42JSUg9NP1bOVUrCyWcTXPsBDHkfaoWSxgkJH8YGU1UCitUGXTDkuk/kNLn0Ik32xN2f5TS2/tgi/QscUm0L8zVBGLIHawhbnOvXTI5/KAG3YJ8vsIitB//3PeyhvYOCKD5WE/6iD/eRVlwW/LhoDXpvnAkMdOqeUp+vTGR2MQhC6AazQaYR+7Pu8QMV17PqR7EsB+PDUkXIbRrboeimw1pfglx6fe5omPj/0D+qTkloL7CfBkhpyxhAgnfE4A36W1UlTGjCL5vqxkXLBoGLI2gsbFITzVKAu1hKoIBGbQysoIBuXNhKQiQvfQfOhZPYKWDQd2q/jHJxDUkMHOE2/l94zzvptKWKghR29Qk8TA2ZBeSMkMJUtP8EE/jISBinDoNynTUBWJrq9fXp0oejhB9ob7AZ70B8Xp/0ETZQm2ZFrXfSqP+Kp5qZB3S85LvgsfkgG5ndxVWsRicIv0zc0lcNoj7A86pPU5yzBUoAcnfgtzkE9p2Mp1HmOr39e3/3NDAbqL1Mx1qkLKiwQWkpWCpypm7LTLGIo+LY3ZswV+2xoDpBfotSi+QtcvhQZ7fJrg= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040375)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(6041248)(20161123558025)(20161123555025)(20161123560025)(20161123564025)(20161123562025)(6072148); SRVR:CY1PR07MB2277; BCL:0; PCL:0; RULEID:; SRVR:CY1PR07MB2277; X-Microsoft-Exchange-Diagnostics: 1; CY1PR07MB2277; 4:sNy1iAkCiGPvMXOhQR9qTR4ZyWsthh6YjAjFTAp31Dof3wyfGzl7CYxWY50kc7jg8XX43KZQZ94glx8bYur4jNb6oqL6VeYbENnYK2+cSgUHFz9mtSQdJL6dnm6h6JZ3RvAKs+p9K8y8+jYIgrVoIpogWPcs6hLnInIqeW0YG8As8aYSkfCE0wGnVUfogEDc9b9SK1sfTSYUqnGJankyy8qlB/LpN99oqDaGSV745MRBZBxTKYq2/wpbsRDheNiLjA9L2Ux8tzhNbvodDUSnIVIl4FEOotZlVP0s7lZcwdEuRmLwrQiFtiHwwROs0NUGZHX/+Qmf7zJ+NcH5bOvbT2mpyZCdzEr4fGqWNn9zL5pJUu+FWH8zAmto1lF7wqQQ1FLtIbjphGwShsGyoBZ27yEFUHE8Ufrp0yWwfV8oNuI3pQQMT2ZNPh0dr1uf2rFBlBlMWVxL20NaxCAZ8VikNVIVDkVSNT7T2oxXOy9Jku/SaPe1PX7zQLjc7VUmY3GlpzPuAsM68LAMrQ1bDxb1jdFb3ZAiiF88vihnHStrFMQnm2jN03ICg/SA3VnQ3A34We+MMtbcuPo+gBPHMDD2z5O3RViCdHGAy5W+TbyUESs= X-Forefront-PRVS: 023495660C X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6009001)(7916002)(39450400003)(2950100002)(6916009)(42882006)(5660300001)(92566002)(4720700003)(33646002)(48376002)(50226002)(6666003)(2906002)(5003940100001)(36756003)(8676002)(50466002)(81166006)(110136004)(38730400002)(4326008)(305945005)(2361001)(53936002)(2351001)(25786008)(6512007)(189998001)(54906002)(47776003)(6506006)(6486002)(66066001)(6116002)(3846002)(50986999)(76176999)(5009440100003)(42186005)(7736002)(7099028)(110426004); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1PR07MB2277; H:lio357.in.caveonetworks.com; FPR:; SPF:None; MLV:nov; PTR:InfoNoRecords; LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR07MB2277; 23:eQP6ga7Nt59MT51Gcmvp2NoJKZ7BA3mFLhh9wjG+X?= pCp0+mqHTzYCKDIRhI8Qnfn4+TwESTq5T+ZtsPG30GZKHRhMO6ppujEzneCSmZKShfJUmenwY/YmYtkeDAJLStah+ZptTBm9/AFWIsw9TjMK6AtS4PImId413pAt0pDSGwECZvdtvkiXB+gk4w1On1QfbHqfY0iecmphlUo8oI4RggEaoiZ/V4q4h5v7+L/WifPWnSZ9qgkdAjxO7wfnqATxnAZ6dfuQpg+FaHivlNq02odIrDkogwLHVABPDGg2Y8+/kT8wAEaZYa98LoOzgRDmnrubP8683wAMSeaJ9sueQCXwGa3g6tfIpBXcs11KvWgLm3RHn1RucUKHl3EQqHFJHnjF91u89ArViB2xuFPOVD0PEKsud/Sb7G/R+R38eBGGi+G2SXY/sMcouKQUosQB3BUR8DlkJ7BPjfcUfORIB+6ZcGRE6mGmwoKqkUibtdiKclkDDqw6cilNA1cxgQypsbeB7CrgEwUfyb5ikRdNMja+/3oZsesMsomsYHdnBylpg5mCMCZqQdZtGaY1Gsew/il5PDIh7J/vet5kDwprjc5MGZljOrUtE0pxHeRthwxMXfxcZ7+JPQeMDDBSrU7G/LvZty4AdRQgtao9TCnw0EwgP5P7Xj6k5N6JvaLyWAqrFViCU6aT+qrYp3u0DUS0Ha2mOjXXlvab/ynSSBgINIvFSZ38BPc95dq9sWlp54IMgYVckQPAf6eVdKLgFU7IA5b1dvZMOtM7oC3ULswjCuOms9yirIEgXc8xlr8RxDURGPGpIeTcz4z8avHOnjUQp/NMcL3i0j1/x2fxziO6Z9aSqg/Kk5Cy0vNw1ROMqB9DbwQCz2zz93QpfKmTAWwbRr07d4UNC4gxQ/gwysZksFQRUWfZviT7ZqkktM/aGhb1l41r+juZLsEyPmGkkBAUf/MCBA05dJzaVn0TwGOdSJ2gRA3PrapZJSwYe7zhzkOw53ig5mnbTvHaJoIxin0F2OT/u8/+02SUPhZhNyhXE6arPvpqSUx/OxagHcijJOwHxLS49yT/7d52KnC+j+5gw1NqFf63LslttRrv432dA== X-Microsoft-Exchange-Diagnostics: 1; CY1PR07MB2277; 6:EjY+4jUO6dC8DRBMy3jkkXhydj7SdJVINq7Wr6cQpG+SkSoMv2W4CDlqR0P6fXzx/yzDt3OKpcO3XUKe+s+w31zumDRuMxTbPGHrNvAUlS/fijlCjUBq7QT4nfh32lB3qOnBqcE9R69K0eYXwIHVGlGXKaMfvLOW+DfHHBcN/feuYiVnK/DXJrKx4a2IDibPzSdkJNJLKPWb72PqDpG0svUfS3cxyOH/Z4DIMNU3ALNwUe9yKL/Z6/QaWUXVSa7wAnZDTpMwHgA3pnidm9kw1DOBD7G+9hnFSG+j1FCjlB9VSSSIReQgoZcqWJ+EOH3xuE4rcjI25twFvkNhsNMSF7TBjgoHqKLMjcoRtPfp2byAFJjrhCo7LM01m+bS5ZzKNRw720KU94DGN1wSf9UPtQ==; 5:VWesjFF87sVfD8X1/Ej/MdwFVQixFdkSLdVQFRZMuMqRLEE108Ncc2m4TCCo3vFHmQjYBIp8P++1e/aiKfZLyn5KFMy5UeWDxiQXnUcg7mLOC5mhvFD7eu05CizwkIuUYD3+hfZO5TlViDraaSOitQ==; 24:IsMWh6EwVAbCqRd6qprgW3cBhQSq2wN+QJU4BCiFizwLWdD1uGESDaxrmqsF5B6wdQZET6nJWnFP/IyTl8WNqD371LAvpM/KPEXnHNi26G4= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; CY1PR07MB2277; 7:7PID9pzFErT0urvATmBH9SN0kwarxH1zA/4VJ0vdi9ZhhieUW6ywFuz6/ZZzZW2G/OQWRb6i5BjwFIwzVRpTVJ8qxeilFmYf4PS8BSvhGDOZW+JE3RSUMezdV4b3FWoqLHlE7rzjQwrvruGTZVmJrRSaJ/bEY3W1wIVR387FWu0kbSEkEk84ihA5yK5EE8IDPz0rKY8TSMaO8i0H8md8/mjWNr0WCWP8m1KjZBNpkxU2di7UoJy4XRx/6684h571twG/ky6Clqr8f4waHG+QH5xjerD5aP4uZGRC3jJbiZVuP+Q46mYpPqKA4SSuEo14elFy5NKcl4j5hxbqEC1tjw== X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2017 11:38:55.4366 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR07MB2277 Subject: [dpdk-dev] [PATCH v2 20/46] net/liquidio: add API to setup Rx queue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Shijith Thotton Signed-off-by: Jerin Jacob Signed-off-by: Derek Chickles Signed-off-by: Venkat Koppula Signed-off-by: Srisivasubramanian S Signed-off-by: Mallesham Jatharakonda --- drivers/net/liquidio/base/lio_hw_defs.h | 3 + drivers/net/liquidio/lio_ethdev.c | 67 +++++++++++++ drivers/net/liquidio/lio_rxtx.c | 168 ++++++++++++++++++++++++++++++++ drivers/net/liquidio/lio_rxtx.h | 56 +++++++++++ drivers/net/liquidio/lio_struct.h | 149 ++++++++++++++++++++++++++++ 5 files changed, 443 insertions(+) diff --git a/drivers/net/liquidio/base/lio_hw_defs.h b/drivers/net/liquidio/base/lio_hw_defs.h index 3201dc5..35d59fd 100644 --- a/drivers/net/liquidio/base/lio_hw_defs.h +++ b/drivers/net/liquidio/base/lio_hw_defs.h @@ -78,6 +78,8 @@ enum lio_card_type { #define LIO_DEV_RUNNING 0xc +#define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \ + ((cfg)->default_config->oq.refill_threshold) #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \ ((cfg)->default_config->num_def_tx_descs) @@ -89,6 +91,7 @@ enum lio_card_type { #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES +#define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES #define LIO_DEVICE_NAME_LEN 32 #define LIO_BASE_MAJOR_VERSION 1 diff --git a/drivers/net/liquidio/lio_ethdev.c b/drivers/net/liquidio/lio_ethdev.c index 194b096..a93fa4a 100644 --- a/drivers/net/liquidio/lio_ethdev.c +++ b/drivers/net/liquidio/lio_ethdev.c @@ -55,6 +55,72 @@ return (res + (res >> 32)) & 0x00000000000000FFul; } +/** + * Setup our receive queue/ringbuffer. This is the + * queue the Octeon uses to send us packets and + * responses. We are given a memory pool for our + * packet buffers that are used to populate the receive + * queue. + * + * @param eth_dev + * Pointer to the structure rte_eth_dev + * @param q_no + * Queue number + * @param num_rx_descs + * Number of entries in the queue + * @param socket_id + * Where to allocate memory + * @param rx_conf + * Pointer to the struction rte_eth_rxconf + * @param mp + * Pointer to the packet pool + * + * @return + * - On success, return 0 + * - On failure, return -1 + */ +static int +lio_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t q_no, + uint16_t num_rx_descs, unsigned int socket_id, + const struct rte_eth_rxconf *rx_conf __rte_unused, + struct rte_mempool *mp) +{ + struct lio_device *lio_dev = LIO_DEV(eth_dev); + struct rte_pktmbuf_pool_private *mbp_priv; + uint32_t fw_mapped_oq; + uint16_t buf_size; + + if (q_no >= lio_dev->nb_rx_queues) { + lio_dev_err(lio_dev, "Invalid rx queue number %u\n", q_no); + return -EINVAL; + } + + lio_dev_dbg(lio_dev, "setting up rx queue %u\n", q_no); + + fw_mapped_oq = lio_dev->linfo.rxpciq[q_no].s.q_no; + + if ((lio_dev->droq[fw_mapped_oq]) && + (num_rx_descs != lio_dev->droq[fw_mapped_oq]->max_count)) { + lio_dev_err(lio_dev, + "Reconfiguring Rx descs not supported. Configure descs to same value %u or restart application\n", + lio_dev->droq[fw_mapped_oq]->max_count); + return -ENOTSUP; + } + + mbp_priv = rte_mempool_get_priv(mp); + buf_size = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM; + + if (lio_setup_droq(lio_dev, fw_mapped_oq, num_rx_descs, buf_size, mp, + socket_id)) { + lio_dev_err(lio_dev, "droq allocation failed\n"); + return -1; + } + + eth_dev->data->rx_queues[q_no] = lio_dev->droq[fw_mapped_oq]; + + return 0; +} + static int lio_dev_configure(struct rte_eth_dev *eth_dev) { struct lio_device *lio_dev = LIO_DEV(eth_dev); @@ -199,6 +265,7 @@ static int lio_dev_configure(struct rte_eth_dev *eth_dev) /* Define our ethernet definitions */ static const struct eth_dev_ops liovf_eth_dev_ops = { .dev_configure = lio_dev_configure, + .rx_queue_setup = lio_dev_rx_queue_setup, }; static void diff --git a/drivers/net/liquidio/lio_rxtx.c b/drivers/net/liquidio/lio_rxtx.c index 7e2202c..942fe9b 100644 --- a/drivers/net/liquidio/lio_rxtx.c +++ b/drivers/net/liquidio/lio_rxtx.c @@ -63,6 +63,174 @@ } /** + * Frees the space for descriptor ring for the droq. + * + * @param lio_dev - pointer to the lio device structure + * @param q_no - droq no. + */ +static void +lio_delete_droq(struct lio_device *lio_dev, uint32_t q_no) +{ + struct lio_droq *droq = lio_dev->droq[q_no]; + + lio_dev_dbg(lio_dev, "OQ[%d]\n", q_no); + + rte_free(droq->recv_buf_list); + droq->recv_buf_list = NULL; + lio_dma_zone_free(lio_dev, droq->info_mz); + lio_dma_zone_free(lio_dev, droq->desc_ring_mz); + + memset(droq, 0, LIO_DROQ_SIZE); +} + +static void * +lio_alloc_info_buffer(struct lio_device *lio_dev, + struct lio_droq *droq, unsigned int socket_id) +{ + droq->info_mz = rte_eth_dma_zone_reserve(lio_dev->eth_dev, + "info_list", droq->q_no, + (droq->max_count * + LIO_DROQ_INFO_SIZE), + RTE_CACHE_LINE_SIZE, + socket_id); + + if (droq->info_mz == NULL) + return NULL; + + droq->info_list_dma = droq->info_mz->phys_addr; + droq->info_alloc_size = droq->info_mz->len; + droq->info_base_addr = (size_t)droq->info_mz->addr; + + return droq->info_mz->addr; +} + +/** + * Allocates space for the descriptor ring for the droq and + * sets the base addr, num desc etc in Octeon registers. + * + * @param lio_dev - pointer to the lio device structure + * @param q_no - droq no. + * @param app_ctx - pointer to application context + * @return Success: 0 Failure: -1 + */ +static int +lio_init_droq(struct lio_device *lio_dev, uint32_t q_no, + uint32_t num_descs, uint32_t desc_size, + struct rte_mempool *mpool, unsigned int socket_id) +{ + uint32_t c_refill_threshold; + uint32_t desc_ring_size; + struct lio_droq *droq; + + lio_dev_dbg(lio_dev, "OQ[%d]\n", q_no); + + droq = lio_dev->droq[q_no]; + droq->lio_dev = lio_dev; + droq->q_no = q_no; + droq->mpool = mpool; + + c_refill_threshold = LIO_OQ_REFILL_THRESHOLD_CFG(lio_dev); + + droq->max_count = num_descs; + droq->buffer_size = desc_size; + + desc_ring_size = droq->max_count * LIO_DROQ_DESC_SIZE; + droq->desc_ring_mz = rte_eth_dma_zone_reserve(lio_dev->eth_dev, + "droq", q_no, + desc_ring_size, + RTE_CACHE_LINE_SIZE, + socket_id); + + if (droq->desc_ring_mz == NULL) { + lio_dev_err(lio_dev, + "Output queue %d ring alloc failed\n", q_no); + return -1; + } + + droq->desc_ring_dma = droq->desc_ring_mz->phys_addr; + droq->desc_ring = (struct lio_droq_desc *)droq->desc_ring_mz->addr; + + lio_dev_dbg(lio_dev, "droq[%d]: desc_ring: virt: 0x%p, dma: %lx\n", + q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma); + lio_dev_dbg(lio_dev, "droq[%d]: num_desc: %d\n", q_no, + droq->max_count); + + droq->info_list = lio_alloc_info_buffer(lio_dev, droq, socket_id); + if (droq->info_list == NULL) { + lio_dev_err(lio_dev, "Cannot allocate memory for info list.\n"); + goto init_droq_fail; + } + + droq->recv_buf_list = rte_zmalloc_socket("recv_buf_list", + (droq->max_count * + LIO_DROQ_RECVBUF_SIZE), + RTE_CACHE_LINE_SIZE, + socket_id); + if (droq->recv_buf_list == NULL) { + lio_dev_err(lio_dev, + "Output queue recv buf list alloc failed\n"); + goto init_droq_fail; + } + + droq->refill_threshold = c_refill_threshold; + + rte_spinlock_init(&droq->lock); + + lio_dev->io_qmask.oq |= (1ULL << q_no); + + return 0; + +init_droq_fail: + lio_delete_droq(lio_dev, q_no); + + return -1; +} + +int +lio_setup_droq(struct lio_device *lio_dev, int oq_no, int num_descs, + int desc_size, struct rte_mempool *mpool, unsigned int socket_id) +{ + struct lio_droq *droq; + + PMD_INIT_FUNC_TRACE(); + + if (lio_dev->droq[oq_no]) { + lio_dev_dbg(lio_dev, "Droq %d in use\n", oq_no); + return 0; + } + + /* Allocate the DS for the new droq. */ + droq = rte_zmalloc_socket("ethdev RX queue", sizeof(*droq), + RTE_CACHE_LINE_SIZE, socket_id); + if (droq == NULL) + return -ENOMEM; + + lio_dev->droq[oq_no] = droq; + + /* Initialize the Droq */ + if (lio_init_droq(lio_dev, oq_no, num_descs, desc_size, mpool, + socket_id)) { + lio_dev_err(lio_dev, "Droq[%u] Initialization Failed\n", oq_no); + rte_free(lio_dev->droq[oq_no]); + lio_dev->droq[oq_no] = NULL; + return -ENOMEM; + } + + lio_dev->num_oqs++; + + lio_dev_dbg(lio_dev, "Total number of OQ: %d\n", lio_dev->num_oqs); + + /* Send credit for octeon output queues. credits are always + * sent after the output queue is enabled. + */ + rte_write32(lio_dev->droq[oq_no]->max_count, + lio_dev->droq[oq_no]->pkts_credit_reg); + rte_wmb(); + + return 0; +} + +/** * lio_init_instr_queue() * @param lio_dev - pointer to the lio device structure. * @param txpciq - queue to be initialized. diff --git a/drivers/net/liquidio/lio_rxtx.h b/drivers/net/liquidio/lio_rxtx.h index 9e2d967..05f4704 100644 --- a/drivers/net/liquidio/lio_rxtx.h +++ b/drivers/net/liquidio/lio_rxtx.h @@ -50,6 +50,58 @@ #define lio_uptime \ (size_t)(rte_get_timer_cycles() / rte_get_timer_hz()) +/** Descriptor format. + * The descriptor ring is made of descriptors which have 2 64-bit values: + * -# Physical (bus) address of the data buffer. + * -# Physical (bus) address of a lio_droq_info structure. + * The device DMA's incoming packets and its information at the address + * given by these descriptor fields. + */ +struct lio_droq_desc { + /** The buffer pointer */ + uint64_t buffer_ptr; + + /** The Info pointer */ + uint64_t info_ptr; +}; + +#define LIO_DROQ_DESC_SIZE (sizeof(struct lio_droq_desc)) + +/** Information about packet DMA'ed by Octeon. + * The format of the information available at Info Pointer after Octeon + * has posted a packet. Not all descriptors have valid information. Only + * the Info field of the first descriptor for a packet has information + * about the packet. + */ +struct lio_droq_info { + /** The Output Receive Header. */ + union octeon_rh rh; + + /** The Length of the packet. */ + uint64_t length; +}; + +#define LIO_DROQ_INFO_SIZE (sizeof(struct lio_droq_info)) + +/** Pointer to data buffer. + * Driver keeps a pointer to the data buffer that it made available to + * the Octeon device. Since the descriptor ring keeps physical (bus) + * addresses, this field is required for the driver to keep track of + * the virtual address pointers. + */ +struct lio_recv_buffer { + /** Packet buffer, including meta data. */ + void *buffer; + + /** Data in the packet buffer. */ + uint8_t *data; + +}; + +#define LIO_DROQ_RECVBUF_SIZE (sizeof(struct lio_recv_buffer)) + +#define LIO_DROQ_SIZE (sizeof(struct lio_droq)) + #define LIO_IQ_SEND_OK 0 #define LIO_IQ_SEND_STOP 1 #define LIO_IQ_SEND_FAILED -1 @@ -458,6 +510,10 @@ enum { return index; } +int lio_setup_droq(struct lio_device *lio_dev, int q_no, int num_descs, + int desc_size, struct rte_mempool *mpool, + unsigned int socket_id); + /** Setup instruction queue zero for the device * @param lio_dev which lio device to setup * diff --git a/drivers/net/liquidio/lio_struct.h b/drivers/net/liquidio/lio_struct.h index 48c4cae..3df79e1 100644 --- a/drivers/net/liquidio/lio_struct.h +++ b/drivers/net/liquidio/lio_struct.h @@ -56,6 +56,150 @@ struct lio_version { uint16_t reserved; }; +/** The Descriptor Ring Output Queue structure. + * This structure has all the information required to implement a + * DROQ. + */ +struct lio_droq { + /** A spinlock to protect access to this ring. */ + rte_spinlock_t lock; + + uint32_t q_no; + + uint32_t pkt_count; + + struct lio_device *lio_dev; + + /** The 8B aligned descriptor ring starts at this address. */ + struct lio_droq_desc *desc_ring; + + /** Index in the ring where the driver should read the next packet */ + uint32_t read_idx; + + /** Index in the ring where Octeon will write the next packet */ + uint32_t write_idx; + + /** Index in the ring where the driver will refill the descriptor's + * buffer + */ + uint32_t refill_idx; + + /** Packets pending to be processed */ + rte_atomic64_t pkts_pending; + + /** Number of descriptors in this ring. */ + uint32_t max_count; + + /** The number of descriptors pending refill. */ + uint32_t refill_count; + + uint32_t refill_threshold; + + /** The 8B aligned info ptrs begin from this address. */ + struct lio_droq_info *info_list; + + /** The receive buffer list. This list has the virtual addresses of the + * buffers. + */ + struct lio_recv_buffer *recv_buf_list; + + /** The size of each buffer pointed by the buffer pointer. */ + uint32_t buffer_size; + + /** Pointer to the mapped packet credit register. + * Host writes number of info/buffer ptrs available to this register + */ + void *pkts_credit_reg; + + /** Pointer to the mapped packet sent register. + * Octeon writes the number of packets DMA'ed to host memory + * in this register. + */ + void *pkts_sent_reg; + + /** DMA mapped address of the DROQ descriptor ring. */ + size_t desc_ring_dma; + + /** Info ptr list are allocated at this virtual address. */ + size_t info_base_addr; + + /** DMA mapped address of the info list */ + size_t info_list_dma; + + /** Allocated size of info list. */ + uint32_t info_alloc_size; + + /** Memory zone **/ + const struct rte_memzone *desc_ring_mz; + const struct rte_memzone *info_mz; + struct rte_mempool *mpool; +}; + +/** Receive Header */ +union octeon_rh { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t rh64; + struct { + uint64_t opcode : 4; + uint64_t subcode : 8; + uint64_t len : 3; /** additional 64-bit words */ + uint64_t reserved : 17; + uint64_t ossp : 32; /** opcode/subcode specific parameters */ + } r; + struct { + uint64_t opcode : 4; + uint64_t subcode : 8; + uint64_t len : 3; /** additional 64-bit words */ + uint64_t extra : 28; + uint64_t vlan : 12; + uint64_t priority : 3; + uint64_t csum_verified : 3; /** checksum verified. */ + uint64_t has_hwtstamp : 1; /** Has hardware timestamp.1 = yes.*/ + uint64_t encap_on : 1; + uint64_t has_hash : 1; /** Has hash (rth or rss). 1 = yes. */ + } r_dh; + struct { + uint64_t opcode : 4; + uint64_t subcode : 8; + uint64_t len : 3; /** additional 64-bit words */ + uint64_t reserved : 8; + uint64_t extra : 25; + uint64_t gmxport : 16; + } r_nic_info; +#else + uint64_t rh64; + struct { + uint64_t ossp : 32; /** opcode/subcode specific parameters */ + uint64_t reserved : 17; + uint64_t len : 3; /** additional 64-bit words */ + uint64_t subcode : 8; + uint64_t opcode : 4; + } r; + struct { + uint64_t has_hash : 1; /** Has hash (rth or rss). 1 = yes. */ + uint64_t encap_on : 1; + uint64_t has_hwtstamp : 1; /** 1 = has hwtstamp */ + uint64_t csum_verified : 3; /** checksum verified. */ + uint64_t priority : 3; + uint64_t vlan : 12; + uint64_t extra : 28; + uint64_t len : 3; /** additional 64-bit words */ + uint64_t subcode : 8; + uint64_t opcode : 4; + } r_dh; + struct { + uint64_t gmxport : 16; + uint64_t extra : 25; + uint64_t reserved : 8; + uint64_t len : 3; /** additional 64-bit words */ + uint64_t subcode : 8; + uint64_t opcode : 4; + } r_nic_info; +#endif +}; + +#define OCTEON_RH_SIZE (sizeof(union octeon_rh)) + /** The txpciq info passed to host from the firmware */ union octeon_txpciq { uint64_t txpciq64; @@ -380,6 +524,11 @@ struct lio_device { /** The singly-linked tail queues of instruction response */ struct lio_response_list response_list; + uint32_t num_oqs; + + /** The DROQ output queues */ + struct lio_droq *droq[LIO_MAX_POSSIBLE_OUTPUT_QUEUES]; + struct lio_io_enable io_qmask; struct lio_sriov_info sriov_info;