From patchwork Tue Feb 28 15:53:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shahaf Shuler X-Patchwork-Id: 20941 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 4211B2BB1; Tue, 28 Feb 2017 16:54:23 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 2A49E2BB1 for ; Tue, 28 Feb 2017 16:54:20 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shahafs@mellanox.com) with ESMTPS (AES256-SHA encrypted); 28 Feb 2017 17:54:15 +0200 Received: from arch010.mtl.labs.mlnx (arch010.mtl.labs.mlnx [10.7.12.210]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v1SFsFi2000552; Tue, 28 Feb 2017 17:54:15 +0200 Received: from arch010.mtl.labs.mlnx (localhost [127.0.0.1]) by arch010.mtl.labs.mlnx (8.14.7/8.14.7) with ESMTP id v1SFsFqM045817; Tue, 28 Feb 2017 17:54:15 +0200 Received: (from root@localhost) by arch010.mtl.labs.mlnx (8.14.7/8.14.7/Submit) id v1SFsFJS045816; Tue, 28 Feb 2017 17:54:15 +0200 From: Shahaf Shuler To: adrien.mazarguil@6wind.com, nelio.laranjeiro@6wind.com Cc: dev@dpdk.org Date: Tue, 28 Feb 2017 17:53:48 +0200 Message-Id: <1488297228-45713-3-git-send-email-shahafs@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1488297228-45713-1-git-send-email-shahafs@mellanox.com> References: <1488297228-45713-1-git-send-email-shahafs@mellanox.com> Subject: [dpdk-dev] [PATCH 2/2] net/mlx5: add hardware TSO support for VXLAN and GRE X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds support for hardware TSO for tunneled packets. Signed-off-by: Shahaf Shuler Acked-by: Nelio Laranjeiro --- drivers/net/mlx5/mlx5_ethdev.c | 4 +++- drivers/net/mlx5/mlx5_rxtx.c | 9 +++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index 3edfd49..4de3595 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -696,7 +696,9 @@ struct priv * if (priv->tso) info->tx_offload_capa |= DEV_TX_OFFLOAD_TCP_TSO; if (priv->tunnel_en) - info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; + info->tx_offload_capa |= (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | + DEV_TX_OFFLOAD_VXLAN_TNL_TSO | + DEV_TX_OFFLOAD_GRE_TNL_TSO); if (priv_get_ifname(priv, &ifname) == 0) info->if_index = if_nametoindex(ifname); /* FIXME: RETA update/query API expects the callee to know the size of diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c index 145daa0..98e7205 100644 --- a/drivers/net/mlx5/mlx5_rxtx.c +++ b/drivers/net/mlx5/mlx5_rxtx.c @@ -488,9 +488,18 @@ (1 << txq->wqe_n) * MLX5_WQE_SIZE); unsigned int copy_b; + const uint64_t is_tunneled = + buf->ol_flags & + (PKT_TX_TUNNEL_GRE | + PKT_TX_TUNNEL_VXLAN); tso_header_sz = buf->l2_len + buf->l3_len + buf->l4_len; + + if (is_tunneled && txq->tunnel_en) { + tso_header_sz += buf->outer_l2_len + + buf->outer_l3_len; + } if (unlikely(tso_header_sz > MLX5_MAX_TSO_HEADER)) break;