From patchwork Fri Nov 25 20:47:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Bieniek X-Patchwork-Id: 17267 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 09416FA42; Fri, 25 Nov 2016 21:48:10 +0100 (CET) Received: from mail-io0-f195.google.com (mail-io0-f195.google.com [209.85.223.195]) by dpdk.org (Postfix) with ESMTP id 2E8B2FA41 for ; Fri, 25 Nov 2016 21:48:07 +0100 (CET) Received: by mail-io0-f195.google.com with SMTP id j92so11532973ioi.0 for ; Fri, 25 Nov 2016 12:48:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=HSMCPARJcEkBJej1DxpTfB3DdaduLERWKf91CQ4UNIw=; b=GZR0R9xLVw1IvJtaCJ1E0nHqrBHDrxt6IAjfzqBgwGjgZA7MdaeTCiCiuAraMmbFE8 gqkYaY/o8/SzYHcsuH7XAQUM6TYe75EgwPhtYOB3+/UQ6WB5w7nyBJoGtf1xc1KkpvBV nXJNeR+X61vdlAxaUFUeZL/5PtuZulBXuLbHNcSGUUCC4u4B4EXVdE6awgj0JzknZFvD x4OK9oXr8splFUAtFGCgEN6IcR6Jd4CFzfydQU/hCDHSqh37EM56QBFZQSea8dHQ/Wnw SzU2gm4/XDb8OTYIX+7jTwODg/pExn+3VedOBMXCZGV7ictwZ350bduJGPsKLCPgsbU4 jmNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=HSMCPARJcEkBJej1DxpTfB3DdaduLERWKf91CQ4UNIw=; b=k7wVfZVGR7dHfYOvLbQM3aZiH77OiDUqTAOuhT5PPHHugi+eVFcXlS+7EiywOy3X2U uFwVicpc9/9sjLjz495RpUbw0OghxPU/8CsJPhqB7NzFKY7I/KL/MEqypfZM6eHtisAC 3iG5rFTI4L+vhGAfRvpepoKgsFyCFtaTwV4sMU35cDpVL+HZQyx4p7nO2gpt5U49QOSK JshH5AHiwQqfEMySqL4aWL9MLHyjzxkHwba4KsbsL3z41xTzUBRO17nOwrxBcxGLDLV0 3+aXSk1ttw+sy1vPvo9TGBg+N0upflldb0aa0lJHQRYyTQDg5O9qZo0Fkg84Scb/h1fB lCmw== X-Gm-Message-State: AKaTC03N0ax/AQjt+XVPhaNJSEEZUkEedx5Rjanps1jnWWhg1keQT1nMe3Gus0zhXZiySg== X-Received: by 10.36.82.85 with SMTP id d82mr8853472itb.95.1480106886586; Fri, 25 Nov 2016 12:48:06 -0800 (PST) Received: from mbieniek_linux.phaedrus.sandvine.com ([64.7.137.182]) by smtp.gmail.com with ESMTPSA id m130sm9001860ioe.34.2016.11.25.12.48.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Nov 2016 12:48:06 -0800 (PST) From: Michael Bieniek To: helin.zhang@intel.com, jingjing.wu@intel.com Cc: dev@dpdk.org, Michael Bieniek Date: Fri, 25 Nov 2016 15:47:35 -0500 Message-Id: <1480106855-3287-1-git-send-email-michaelbieniekdpdk@gmail.com> X-Mailer: git-send-email 2.4.11 Subject: [dpdk-dev] [PATCH] i40evf: add set maximum frame size support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This adds the ability to set maximum frame size for an i40e virtual interface. This patch is based on the i40e physical function maximum frame size implementation. This was tested on an system configured with multiple i40e virtual functions. Verified that the MTU was configurable and that sending packets greater than the configured MTU resulted in a drop. Signed-off-by: Michael Bieniek Signed-off-by: Michael Bieniek Acked-by: Jingjing Wu --- drivers/net/i40e/i40e_ethdev_vf.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index aa306d6..8477c98 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -158,6 +158,7 @@ i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id); static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev, uint8_t *msg, uint16_t msglen); +static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t); /* Default hash key buffer for RSS */ static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1]; @@ -225,6 +226,7 @@ static const struct eth_dev_ops i40evf_eth_dev_ops = { .reta_query = i40evf_dev_rss_reta_query, .rss_hash_update = i40evf_dev_rss_hash_update, .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get, + .mtu_set = i40evf_dev_mtu_set, }; /* @@ -2635,3 +2637,34 @@ i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev, return 0; } + +static int +i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_eth_dev_data *dev_data = dev->data; + uint32_t frame_size = mtu + ETHER_HDR_LEN + + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE; + int ret = 0; + + /* check if mtu is within the allowed range */ + if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX)) + return -EINVAL; + + /* mtu setting is forbidden if port is started */ + if (dev_data->dev_started) { + PMD_DRV_LOG(ERR, + "port %d must be stopped before configuration\n", + dev_data->port_id); + return -EBUSY; + } + + if (frame_size > ETHER_MAX_LEN) + dev_data->dev_conf.rxmode.jumbo_frame = 1; + else + dev_data->dev_conf.rxmode.jumbo_frame = 0; + + dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size; + + return ret; +}