From patchwork Thu Apr 21 13:08:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Jastrzebski X-Patchwork-Id: 12186 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id C2B9D38EB; Thu, 21 Apr 2016 15:08:29 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 063C038EB for ; Thu, 21 Apr 2016 15:08:27 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP; 21 Apr 2016 06:08:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,512,1455004800"; d="scan'208";a="949947147" Received: from pczapiex-mobl.ger.corp.intel.com (HELO Sent) ([10.217.248.212]) by fmsmga001.fm.intel.com with SMTP; 21 Apr 2016 06:08:24 -0700 Received: by Sent (sSMTP sendmail emulation); Thu, 21 Apr 2016 15:08:23 +0200 From: Michal Jastrzebski To: cristian.dumitrescu@intel.com, roy.fan.zhang@intel.com, jasvinder.singh@intel.com Cc: dev@dpdk.org, Slawomir Mrozowicz Date: Thu, 21 Apr 2016 15:08:13 +0200 Message-Id: <1461244093-2008-3-git-send-email-michalx.k.jastrzebski@intel.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1461244093-2008-1-git-send-email-michalx.k.jastrzebski@intel.com> References: <1461244093-2008-1-git-send-email-michalx.k.jastrzebski@intel.com> Subject: [dpdk-dev] [PATCH v3] examples/qos_sched: fix bad bit shift operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Slawomir Mrozowicz Fix issue reported by Coverity. Coverity ID 30690: Bad bit shift operation large_shift: In expression 1ULL << i, left shifting by more than 63 bits has undefined behavior. The shift amount, i, is as much as 127. Fixes: de3cfa2c9823 ("sched: initial import") Signed-off-by: Slawomir Mrozowicz --- examples/qos_sched/args.c | 84 +++++++++++++++++++++++++++++------------------ 1 file changed, 52 insertions(+), 32 deletions(-) diff --git a/examples/qos_sched/args.c b/examples/qos_sched/args.c index 3e7fd08..cd077ba 100644 --- a/examples/qos_sched/args.c +++ b/examples/qos_sched/args.c @@ -53,7 +53,7 @@ static uint32_t app_master_core = 1; static uint32_t app_numa_mask; -static uint64_t app_used_core_mask = 0; +static int app_used_core_mask[RTE_MAX_LCORE]; static uint64_t app_used_port_mask = 0; static uint64_t app_used_rx_port_mask = 0; static uint64_t app_used_tx_port_mask = 0; @@ -115,22 +115,23 @@ static inline int str_is(const char *str, const char *is) return strcmp(str, is) == 0; } -/* returns core mask used by DPDK */ -static uint64_t -app_eal_core_mask(void) +/* compare used core with eal configuration, + returns: + 1 if equal + 0 if differ */ +static int +app_eal_core_check(void) { - uint32_t i; - uint64_t cm = 0; + uint16_t i; + int ret = 1; struct rte_config *cfg = rte_eal_get_configuration(); - for (i = 0; i < RTE_MAX_LCORE; i++) { - if (cfg->lcore_role[i] == ROLE_RTE) - cm |= (1ULL << i); + for (i = 0; i < RTE_MAX_LCORE && ret; i++) { + if ((cfg->lcore_role[i] == ROLE_RTE) != app_used_core_mask[i]) + ret = 0; } - cm |= (1ULL << cfg->master_lcore); - - return cm; + return ret; } @@ -292,14 +293,9 @@ app_parse_flow_conf(const char *conf_str) app_used_tx_port_mask |= mask; app_used_port_mask |= mask; - mask = 1lu << pconf->rx_core; - app_used_core_mask |= mask; - - mask = 1lu << pconf->wt_core; - app_used_core_mask |= mask; - - mask = 1lu << pconf->tx_core; - app_used_core_mask |= mask; + app_used_core_mask[pconf->rx_core] = 1; + app_used_core_mask[pconf->wt_core] = 1; + app_used_core_mask[pconf->tx_core] = 1; nb_pfc++; @@ -335,7 +331,7 @@ app_parse_args(int argc, char **argv) int option_index; const char *optname; char *prgname = argv[0]; - uint32_t i, nb_lcores; + uint16_t i, j, k, nb_lcores; static struct option lgopts[] = { { "pfc", 1, 0, 0 }, @@ -349,6 +345,9 @@ app_parse_args(int argc, char **argv) { NULL, 0, 0, 0 } }; + for (i = 0; i < RTE_MAX_LCORE; i++) + app_used_core_mask[i] = 0; + /* initialize EAL first */ ret = rte_eal_init(argc, argv); if (ret < 0) @@ -436,19 +435,40 @@ app_parse_args(int argc, char **argv) } /* check master core index validity */ - for(i = 0; i <= app_master_core; i++) { - if (app_used_core_mask & (1u << app_master_core)) { - RTE_LOG(ERR, APP, "Master core index is not configured properly\n"); - app_usage(prgname); - return -1; - } + if (app_used_core_mask[app_master_core] == 1) { + RTE_LOG(ERR, APP, + "Master core index is not configured properly\n"); + app_usage(prgname); + return -1; } - app_used_core_mask |= 1u << app_master_core; + app_used_core_mask[app_master_core] = 1; + + if ((app_eal_core_check() == 0) || + (app_master_core != rte_get_master_lcore())) { + + char used_hexstr[RTE_MAX_LCORE/4+1]; + char conf_hexstr[RTE_MAX_LCORE/4+1]; + int used_byte, conf_byte; + struct rte_config *cfg = rte_eal_get_configuration(); + + for (i = 0; i < RTE_MAX_LCORE/4; i++) { + used_byte = 0; + conf_byte = 0; + for (j = 0; j < 3; j++) { + k = 4 * (RTE_MAX_LCORE/4 - i - 1) + j; + used_byte += app_used_core_mask[k] << j; + conf_byte += + ((cfg->lcore_role[k] == + ROLE_RTE)?1:0) << j; + } + sprintf(&used_hexstr[i], "%1x", used_byte); + sprintf(&conf_hexstr[i], "%1x", used_byte); + } + + RTE_LOG(ERR, APP, "EAL core mask not configured properly\n"); + RTE_LOG(ERR, APP, " must be : %s\n", used_hexstr); + RTE_LOG(ERR, APP, " instead of: %s\n", conf_hexstr); - if ((app_used_core_mask != app_eal_core_mask()) || - (app_master_core != rte_get_master_lcore())) { - RTE_LOG(ERR, APP, "EAL core mask not configured properly, must be %" PRIx64 - " instead of %" PRIx64 "\n" , app_used_core_mask, app_eal_core_mask()); return -1; }