From patchwork Tue Feb 16 20:37:03 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Marchand X-Patchwork-Id: 10556 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id C6247C320; Tue, 16 Feb 2016 21:37:19 +0100 (CET) Received: from mail-wm0-f46.google.com (mail-wm0-f46.google.com [74.125.82.46]) by dpdk.org (Postfix) with ESMTP id 4A60BC314 for ; Tue, 16 Feb 2016 21:37:17 +0100 (CET) Received: by mail-wm0-f46.google.com with SMTP id b205so127244040wmb.1 for ; Tue, 16 Feb 2016 12:37:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mgGhhrO1ZyPo9Vp8456VXjkOyAj8Q79nkC/TyEOJFI4=; b=BNCrfaBXpe8lfG1oiucKgk43Rfqixb3icckgQpt0LCYg82cI9u8gotWmDr3maEucAQ zHt4VZPD3SBIiohBAmytbgCBORQJvs7Bk2lgVYF4BP3cRCM8RHzvKVM59qtMeJY9+G22 ShSNntjm2tcwVSoAL94fCQC97INAWXM2tjBjK1w1JHUAoRMfyaXDgeiuiKxz9fqe6BZx nlavqoXxADfB0w7ClOLAUJJI/tI8qbORR+NHczFUz/pzAI5uHpvsEnPEHUTEM16TvYDe dQTjGLwAFQrZJd9knAtqpXu6GpcXZMYFEfZsJFdmzyMvHF/gmuiMWrEBPB5Khhft3iYX qggA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mgGhhrO1ZyPo9Vp8456VXjkOyAj8Q79nkC/TyEOJFI4=; b=JMX/0g5TXzkmPpBcrg3FdbuqoCKVvqbnElbSid2rN5JCUnpwUpqn2C8XlQkDbSTIDZ vDFV4RQtwyZCDL/eR90umViyMaA7bLPCMDfp7JtJxMhXp4ReLrpxYqOVQrgubnFeFExu ee69rwBoFyDa866l/gtFgWNL4j57x6VPYpV2jJN3eom7BeQ7VbU1eXAJqVzHvSeoZEc+ TU3h/6izo1kGn9qnYHRSiZ48jPxSQ15nwkBehtCmQxISwPlMyZVQXx8gUZ0u58PznT3b tuovkjgaS3j4NiKeL1rzd+kovUpgNexr7vY+cYbGoepDn/lBn/K3wArMzmq229FEwLAC V1vQ== X-Gm-Message-State: AG10YOTJk9/RZ7Tq0cMuWwB62gWrbNM4mX76YAs9bWuhQBemud+ep2HYEz3kt8A4VKOQZ7el X-Received: by 10.194.174.73 with SMTP id bq9mr24412096wjc.145.1455655037168; Tue, 16 Feb 2016 12:37:17 -0800 (PST) Received: from gloops.dev.6wind.com (guy78-1-82-235-116-147.fbx.proxad.net. [82.235.116.147]) by smtp.gmail.com with ESMTPSA id lc3sm31813646wjb.7.2016.02.16.12.37.15 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 16 Feb 2016 12:37:16 -0800 (PST) From: David Marchand To: dev@dpdk.org Date: Tue, 16 Feb 2016 21:37:03 +0100 Message-Id: <1455655024-5164-4-git-send-email-david.marchand@6wind.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455655024-5164-1-git-send-email-david.marchand@6wind.com> References: <1455542666-28895-1-git-send-email-david.marchand@6wind.com> <1455655024-5164-1-git-send-email-david.marchand@6wind.com> Subject: [dpdk-dev] [PATCH v4 3/4] eal: introduce pci ioport api X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Most of the code is inspired on virtio driver. rte_pci_ioport structure is filled at map time with anything needed for later read / write calls. At the moment, base field is used to store a x86 ioport (uint16_t) and will be reused for other arches. Signed-off-by: David Marchand Tested-by: Santosh Shukla Reviewed-by: Yuanhan Liu --- Changes since v3: - renamed "offset" field in rte_pci_ioport structure as "base" Changes since v2: - removed remaining reference to rte_ioport_t Changes since v1: - dropped rte_ioport and removed the arch headers, if performance is an issue, we will see how to enhance this in later patches - rte_pci_ioport object now reaches driver implementation (uio / vfio) - sanity checks are in uio map function, no reason to have those checks in read/write functions --- lib/librte_eal/bsdapp/eal/eal_pci.c | 135 +++++++++++++++++++ lib/librte_eal/bsdapp/eal/rte_eal_version.map | 4 + lib/librte_eal/common/include/rte_pci.h | 65 +++++++++ lib/librte_eal/linuxapp/eal/eal_pci.c | 170 ++++++++++++++++++++++++ lib/librte_eal/linuxapp/eal/eal_pci_init.h | 16 +++ lib/librte_eal/linuxapp/eal/eal_pci_uio.c | 132 +++++++++++++++++- lib/librte_eal/linuxapp/eal/eal_pci_vfio.c | 37 ++++++ lib/librte_eal/linuxapp/eal/rte_eal_version.map | 4 + 8 files changed, 560 insertions(+), 3 deletions(-) diff --git a/lib/librte_eal/bsdapp/eal/eal_pci.c b/lib/librte_eal/bsdapp/eal/eal_pci.c index 95c32c1..77e9cb3 100644 --- a/lib/librte_eal/bsdapp/eal/eal_pci.c +++ b/lib/librte_eal/bsdapp/eal/eal_pci.c @@ -51,6 +51,11 @@ #include #include +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) +#include +#include +#endif + #include #include #include @@ -479,6 +484,136 @@ int rte_eal_pci_write_config(const struct rte_pci_device *dev, return -1; } +int +rte_eal_pci_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p) +{ + int ret; + + switch (dev->kdrv) { +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + case RTE_KDRV_NIC_UIO: + if ((uintptr_t) dev->mem_resource[bar].addr <= UINT16_MAX) { + p->base = (uintptr_t)dev->mem_resource[bar].addr; + ret = 0; + } else + ret = -1; + break; +#endif + default: + ret = -1; + break; + } + + if (!ret) + p->dev = dev; + + return ret; +} + +static void +pci_uio_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset) +{ +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + uint8_t *d; + int size; + unsigned short reg = p->base + offset; + + for (d = data; len > 0; d += size, reg += size, len -= size) { + if (len >= 4) { + size = 4; + *(uint32_t *)d = inl(reg); + } else if (len >= 2) { + size = 2; + *(uint16_t *)d = inw(reg); + } else { + size = 1; + *d = inb(reg); + } + } +#else + RTE_SET_USED(p); + RTE_SET_USED(data); + RTE_SET_USED(len); + RTE_SET_USED(offset); +#endif +} + +void +rte_eal_pci_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset) +{ + switch (p->dev->kdrv) { + case RTE_KDRV_NIC_UIO: + pci_uio_ioport_read(p, data, len, offset); + break; + default: + break; + } +} + +static void +pci_uio_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset) +{ +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + const uint8_t *s; + int size; + unsigned short reg = p->base + offset; + + for (s = data; len > 0; s += size, reg += size, len -= size) { + if (len >= 4) { + size = 4; + outl(*(const uint32_t *)s, reg); + } else if (len >= 2) { + size = 2; + outw(*(const uint16_t *)s, reg); + } else { + size = 1; + outb(*s, reg); + } + } +#else + RTE_SET_USED(p); + RTE_SET_USED(data); + RTE_SET_USED(len); + RTE_SET_USED(offset); +#endif +} + +void +rte_eal_pci_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset) +{ + switch (p->dev->kdrv) { + case RTE_KDRV_NIC_UIO: + pci_uio_ioport_write(p, data, len, offset); + break; + default: + break; + } +} + +int +rte_eal_pci_ioport_unmap(struct rte_pci_ioport *p) +{ + int ret; + + switch (p->dev->kdrv) { +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + case RTE_KDRV_NIC_UIO: + ret = 0; + break; +#endif + default: + ret = -1; + break; + } + + return ret; +} + /* Init the PCI EAL subsystem */ int rte_eal_pci_init(void) diff --git a/lib/librte_eal/bsdapp/eal/rte_eal_version.map b/lib/librte_eal/bsdapp/eal/rte_eal_version.map index 1a96203..4f93ab7 100644 --- a/lib/librte_eal/bsdapp/eal/rte_eal_version.map +++ b/lib/librte_eal/bsdapp/eal/rte_eal_version.map @@ -140,6 +140,10 @@ DPDK_2.3 { global: rte_cpu_get_flag_name; + rte_eal_pci_ioport_map; + rte_eal_pci_ioport_read; + rte_eal_pci_ioport_unmap; + rte_eal_pci_ioport_write; rte_eal_pci_map_device; rte_eal_pci_unmap_device; diff --git a/lib/librte_eal/common/include/rte_pci.h b/lib/librte_eal/common/include/rte_pci.h index 1508ea9..067e084 100644 --- a/lib/librte_eal/common/include/rte_pci.h +++ b/lib/librte_eal/common/include/rte_pci.h @@ -512,6 +512,71 @@ int rte_eal_pci_read_config(const struct rte_pci_device *device, int rte_eal_pci_write_config(const struct rte_pci_device *device, const void *buf, size_t len, off_t offset); +/** + * A structure used to access io resources for a pci device. + * rte_pci_ioport is arch, os, driver specific, and should not be used outside + * of pci ioport api. + */ +struct rte_pci_ioport { + struct rte_pci_device *dev; + uint64_t base; +}; + +/** + * Initialises a rte_pci_ioport object for a pci device io resource. + * This object is then used to gain access to those io resources (see below). + * + * @param dev + * A pointer to a rte_pci_device structure describing the device. + * to use + * @param bar + * Index of the io pci resource we want to access. + * @param p + * The rte_pci_ioport object to be initialized. + * @return + * 0 on success, negative on error. + */ +int rte_eal_pci_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p); + +/** + * Release any resources used in a rte_pci_ioport object. + * + * @param p + * The rte_pci_ioport object to be uninitialized. + */ +int rte_eal_pci_ioport_unmap(struct rte_pci_ioport *p); + +/** + * Read from a io pci resource. + * + * @param p + * The rte_pci_ioport object from which we want to read. + * @param data + * A data buffer where the bytes should be read into + * @param len + * The length of the data buffer. + * @param offset + * The offset into the pci io resource. + */ +void rte_eal_pci_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset); + +/** + * Write to a io pci resource. + * + * @param p + * The rte_pci_ioport object to which we want to write. + * @param data + * A data buffer where the bytes should be read into + * @param len + * The length of the data buffer. + * @param offset + * The offset into the pci io resource. + */ +void rte_eal_pci_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset); + #ifdef RTE_PCI_CONFIG /** * Set special config space registers for performance purpose. diff --git a/lib/librte_eal/linuxapp/eal/eal_pci.c b/lib/librte_eal/linuxapp/eal/eal_pci.c index db947da..4346973 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci.c @@ -621,6 +621,176 @@ int rte_eal_pci_write_config(const struct rte_pci_device *device, } } +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) +static int +pci_ioport_map(struct rte_pci_device *dev, int bar __rte_unused, + struct rte_pci_ioport *p) +{ + uint16_t start, end; + FILE *fp; + char *line = NULL; + char pci_id[16]; + int found = 0; + size_t linesz; + + snprintf(pci_id, sizeof(pci_id), PCI_PRI_FMT, + dev->addr.domain, dev->addr.bus, + dev->addr.devid, dev->addr.function); + + fp = fopen("/proc/ioports", "r"); + if (fp == NULL) { + RTE_LOG(ERR, EAL, "%s(): can't open ioports\n", __func__); + return -1; + } + + while (getdelim(&line, &linesz, '\n', fp) > 0) { + char *ptr = line; + char *left; + int n; + + n = strcspn(ptr, ":"); + ptr[n] = 0; + left = &ptr[n + 1]; + + while (*left && isspace(*left)) + left++; + + if (!strncmp(left, pci_id, strlen(pci_id))) { + found = 1; + + while (*ptr && isspace(*ptr)) + ptr++; + + sscanf(ptr, "%04hx-%04hx", &start, &end); + + break; + } + } + + free(line); + fclose(fp); + + if (!found) + return -1; + + dev->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN; + p->base = start; + RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%x\n", start); + + return 0; +} +#endif + +int +rte_eal_pci_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p) +{ + int ret; + + switch (dev->kdrv) { +#ifdef VFIO_PRESENT + case RTE_KDRV_VFIO: + ret = -1; + if (pci_vfio_is_enabled()) + ret = pci_vfio_ioport_map(dev, bar, p); + break; +#endif + case RTE_KDRV_IGB_UIO: + case RTE_KDRV_UIO_GENERIC: + ret = pci_uio_ioport_map(dev, bar, p); + break; + default: +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + /* special case for x86 ... */ + ret = pci_ioport_map(dev, bar, p); +#else + ret = -1; +#endif + break; + } + + if (!ret) + p->dev = dev; + + return ret; +} + +void +rte_eal_pci_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset) +{ + switch (p->dev->kdrv) { +#ifdef VFIO_PRESENT + case RTE_KDRV_VFIO: + pci_vfio_ioport_read(p, data, len, offset); + break; +#endif + case RTE_KDRV_IGB_UIO: + case RTE_KDRV_UIO_GENERIC: + pci_uio_ioport_read(p, data, len, offset); + break; + default: +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + /* special case for x86 ... */ + pci_uio_ioport_read(p, data, len, offset); +#endif + break; + } +} + +void +rte_eal_pci_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset) +{ + switch (p->dev->kdrv) { +#ifdef VFIO_PRESENT + case RTE_KDRV_VFIO: + pci_vfio_ioport_write(p, data, len, offset); + break; +#endif + case RTE_KDRV_IGB_UIO: + case RTE_KDRV_UIO_GENERIC: + pci_uio_ioport_write(p, data, len, offset); + break; + default: +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + /* special case for x86 ... */ + pci_uio_ioport_write(p, data, len, offset); +#endif + break; + } +} + +int +rte_eal_pci_ioport_unmap(struct rte_pci_ioport *p) +{ + int ret; + + switch (p->dev->kdrv) { +#ifdef VFIO_PRESENT + case RTE_KDRV_VFIO: + ret = -1; + if (pci_vfio_is_enabled()) + ret = pci_vfio_ioport_unmap(p); + break; +#endif + case RTE_KDRV_IGB_UIO: + case RTE_KDRV_UIO_GENERIC: + ret = pci_uio_ioport_unmap(p); + break; + default: +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + /* special case for x86 ... nothing to do */ + ret = 0; +#else + ret = -1; +#endif + break; + } + + return ret; +} + /* Init the PCI EAL subsystem */ int rte_eal_pci_init(void) diff --git a/lib/librte_eal/linuxapp/eal/eal_pci_init.h b/lib/librte_eal/linuxapp/eal/eal_pci_init.h index a17c708..7011753 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci_init.h +++ b/lib/librte_eal/linuxapp/eal/eal_pci_init.h @@ -54,6 +54,14 @@ int pci_uio_read_config(const struct rte_intr_handle *intr_handle, int pci_uio_write_config(const struct rte_intr_handle *intr_handle, const void *buf, size_t len, off_t offs); +int pci_uio_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p); +void pci_uio_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset); +void pci_uio_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset); +int pci_uio_ioport_unmap(struct rte_pci_ioport *p); + #ifdef VFIO_PRESENT #define VFIO_MAX_GROUPS 64 @@ -68,6 +76,14 @@ int pci_vfio_read_config(const struct rte_intr_handle *intr_handle, int pci_vfio_write_config(const struct rte_intr_handle *intr_handle, const void *buf, size_t len, off_t offs); +int pci_vfio_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p); +void pci_vfio_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset); +void pci_vfio_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset); +int pci_vfio_ioport_unmap(struct rte_pci_ioport *p); + /* map VFIO resource prototype */ int pci_vfio_map_resource(struct rte_pci_device *dev); int pci_vfio_get_group_fd(int iommu_group_fd); diff --git a/lib/librte_eal/linuxapp/eal/eal_pci_uio.c b/lib/librte_eal/linuxapp/eal/eal_pci_uio.c index ac50e13..db22d31 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci_uio.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci_uio.c @@ -39,6 +39,10 @@ #include #include +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) +#include +#endif + #include #include #include @@ -145,7 +149,7 @@ pci_mknod_uio_dev(const char *sysfs_uio_path, unsigned uio_num) */ static int pci_get_uio_dev(struct rte_pci_device *dev, char *dstbuf, - unsigned int buflen) + unsigned int buflen, int create) { struct rte_pci_addr *loc = &dev->addr; unsigned int uio_num; @@ -208,7 +212,7 @@ pci_get_uio_dev(struct rte_pci_device *dev, char *dstbuf, return -1; /* create uio device if we've been asked to */ - if (internal_config.create_uio_dev && + if (internal_config.create_uio_dev && create && pci_mknod_uio_dev(dstbuf, uio_num) < 0) RTE_LOG(WARNING, EAL, "Cannot create /dev/uio%u\n", uio_num); @@ -245,7 +249,7 @@ pci_uio_alloc_resource(struct rte_pci_device *dev, loc = &dev->addr; /* find uio resource */ - uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname)); + uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 1); if (uio_num < 0) { RTE_LOG(WARNING, EAL, " "PCI_PRI_FMT" not managed by UIO driver, " "skipping\n", loc->domain, loc->bus, loc->devid, loc->function); @@ -363,3 +367,125 @@ error: rte_free(maps[map_idx].path); return -1; } + +int +pci_uio_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p) +{ +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + char dirname[PATH_MAX]; + char filename[PATH_MAX]; + int uio_num; + unsigned long start; + + uio_num = pci_get_uio_dev(dev, dirname, sizeof(dirname), 0); + if (uio_num < 0) + return -1; + + /* get portio start */ + snprintf(filename, sizeof(filename), + "%s/portio/port%d/start", dirname, bar); + if (eal_parse_sysfs_value(filename, &start) < 0) { + RTE_LOG(ERR, EAL, "%s(): cannot parse portio start\n", + __func__); + return -1; + } + /* ensure we don't get anything funny here, read/write will cast to + * uin16_t */ + if (start > UINT16_MAX) + return -1; + + /* FIXME only for primary process ? */ + if (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) { + + snprintf(filename, sizeof(filename), "/dev/uio%u", uio_num); + dev->intr_handle.fd = open(filename, O_RDWR); + if (dev->intr_handle.fd < 0) { + RTE_LOG(ERR, EAL, "Cannot open %s: %s\n", + filename, strerror(errno)); + return -1; + } + dev->intr_handle.type = RTE_INTR_HANDLE_UIO; + } + + RTE_LOG(DEBUG, EAL, "PCI Port IO found start=0x%lx\n", start); + + p->base = start; + return 0; +#else + RTE_SET_USED(dev); + RTE_SET_USED(bar); + RTE_SET_USED(p); + return -1; +#endif +} + +void +pci_uio_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset) +{ +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + uint8_t *d; + int size; + unsigned short reg = p->base + offset; + + for (d = data; len > 0; d += size, reg += size, len -= size) { + if (len >= 4) { + size = 4; + *(uint32_t *)d = inl(reg); + } else if (len >= 2) { + size = 2; + *(uint16_t *)d = inw(reg); + } else { + size = 1; + *d = inb(reg); + } + } +#else + RTE_SET_USED(p); + RTE_SET_USED(data); + RTE_SET_USED(len); + RTE_SET_USED(offset); +#endif +} + +void +pci_uio_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset) +{ +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + const uint8_t *s; + int size; + unsigned short reg = p->base + offset; + + for (s = data; len > 0; s += size, reg += size, len -= size) { + if (len >= 4) { + size = 4; + outl_p(*(const uint32_t *)s, reg); + } else if (len >= 2) { + size = 2; + outw_p(*(const uint16_t *)s, reg); + } else { + size = 1; + outb_p(*s, reg); + } + } +#else + RTE_SET_USED(p); + RTE_SET_USED(data); + RTE_SET_USED(len); + RTE_SET_USED(offset); +#endif +} + +int +pci_uio_ioport_unmap(struct rte_pci_ioport *p) +{ + RTE_SET_USED(p); +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686) + /* FIXME close intr fd ? */ + return 0; +#else + return -1; +#endif +} diff --git a/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c b/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c index a6c7e16..ffa2dd0 100644 --- a/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c +++ b/lib/librte_eal/linuxapp/eal/eal_pci_vfio.c @@ -976,6 +976,43 @@ pci_vfio_map_resource(struct rte_pci_device *dev) } int +pci_vfio_ioport_map(struct rte_pci_device *dev, int bar, + struct rte_pci_ioport *p) +{ + RTE_SET_USED(dev); + RTE_SET_USED(bar); + RTE_SET_USED(p); + return -1; +} + +void +pci_vfio_ioport_read(struct rte_pci_ioport *p, + void *data, size_t len, off_t offset) +{ + RTE_SET_USED(p); + RTE_SET_USED(data); + RTE_SET_USED(len); + RTE_SET_USED(offset); +} + +void +pci_vfio_ioport_write(struct rte_pci_ioport *p, + const void *data, size_t len, off_t offset) +{ + RTE_SET_USED(p); + RTE_SET_USED(data); + RTE_SET_USED(len); + RTE_SET_USED(offset); +} + +int +pci_vfio_ioport_unmap(struct rte_pci_ioport *p) +{ + RTE_SET_USED(p); + return -1; +} + +int pci_vfio_enable(void) { /* initialize group list */ diff --git a/lib/librte_eal/linuxapp/eal/rte_eal_version.map b/lib/librte_eal/linuxapp/eal/rte_eal_version.map index 440fac2..e8d8660 100644 --- a/lib/librte_eal/linuxapp/eal/rte_eal_version.map +++ b/lib/librte_eal/linuxapp/eal/rte_eal_version.map @@ -143,6 +143,10 @@ DPDK_2.3 { global: rte_cpu_get_flag_name; + rte_eal_pci_ioport_map; + rte_eal_pci_ioport_read; + rte_eal_pci_ioport_unmap; + rte_eal_pci_ioport_write; rte_eal_pci_map_device; rte_eal_pci_unmap_device;