diff --git a/drivers/net/fm10k/base/fm10k_mbx.h b/drivers/net/fm10k/base/fm10k_mbx.h
index e642c2f..edc57df 100644
--- a/drivers/net/fm10k/base/fm10k_mbx.h
+++ b/drivers/net/fm10k/base/fm10k_mbx.h
@@ -48,7 +48,6 @@ struct fm10k_mbx_info;
 /* XOR provides means of switching from Tx to Rx FIFO */
 #define FM10K_MBMEM_PF_XOR	(FM10K_MBMEM_SM(0) ^ FM10K_MBMEM_PF(0))
 #define FM10K_MBX(_n)		((_n) + 0x18800)
-#define FM10K_MBX_OWNER				0x00000001
 #define FM10K_MBX_REQ				0x00000002
 #define FM10K_MBX_ACK				0x00000004
 #define FM10K_MBX_REQ_INTERRUPT			0x00000008
@@ -213,7 +212,6 @@ enum fm10k_msg_type {
 /* version number for switch manager mailboxes */
 #define FM10K_SM_MBX_VERSION		1
 #define FM10K_SM_MBX_FIFO_LEN		(FM10K_MBMEM_PF_XOR - 1)
-#define FM10K_SM_MBX_FIFO_HDR_LEN	1
 
 /* offsets shared between all SM FIFO headers */
 #define FM10K_MSG_SM_TAIL_SHIFT			0
@@ -233,18 +231,13 @@ enum fm10k_msg_type {
  */
 #define FM10K_MBX_ERR(_n) ((_n) - 512)
 #define FM10K_MBX_ERR_NO_MBX		FM10K_MBX_ERR(0x01)
-#define FM10K_MBX_ERR_NO_MSG		FM10K_MBX_ERR(0x02)
 #define FM10K_MBX_ERR_NO_SPACE		FM10K_MBX_ERR(0x03)
-#define FM10K_MBX_ERR_LOCK		FM10K_MBX_ERR(0x04)
 #define FM10K_MBX_ERR_TAIL		FM10K_MBX_ERR(0x05)
 #define FM10K_MBX_ERR_HEAD		FM10K_MBX_ERR(0x06)
-#define FM10K_MBX_ERR_DST		FM10K_MBX_ERR(0x07)
 #define FM10K_MBX_ERR_SRC		FM10K_MBX_ERR(0x08)
 #define FM10K_MBX_ERR_TYPE		FM10K_MBX_ERR(0x09)
-#define FM10K_MBX_ERR_LEN		FM10K_MBX_ERR(0x0A)
 #define FM10K_MBX_ERR_SIZE		FM10K_MBX_ERR(0x0B)
 #define FM10K_MBX_ERR_BUSY		FM10K_MBX_ERR(0x0C)
-#define FM10K_MBX_ERR_VALUE		FM10K_MBX_ERR(0x0D)
 #define FM10K_MBX_ERR_RSVD0		FM10K_MBX_ERR(0x0E)
 #define FM10K_MBX_ERR_CRC		FM10K_MBX_ERR(0x0F)
 
diff --git a/drivers/net/fm10k/base/fm10k_pf.h b/drivers/net/fm10k/base/fm10k_pf.h
index ee8527a..c84b1bc 100644
--- a/drivers/net/fm10k/base/fm10k_pf.h
+++ b/drivers/net/fm10k/base/fm10k_pf.h
@@ -140,10 +140,6 @@ struct fm10k_swapi_1588_clock_owner {
 #pragma pack()
 #endif /* C99 */
 
-#define FM10K_PF_MSG_LPORT_CREATE_HANDLER(func) \
-	FM10K_MSG_HANDLER(FM10K_PF_MSG_ID_LPORT_CREATE, NULL, func)
-#define FM10K_PF_MSG_LPORT_DELETE_HANDLER(func) \
-	FM10K_MSG_HANDLER(FM10K_PF_MSG_ID_LPORT_DELETE, NULL, func)
 s32 fm10k_msg_lport_map_pf(struct fm10k_hw *, u32 **, struct fm10k_mbx_info *);
 extern const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[];
 #define FM10K_PF_MSG_LPORT_MAP_HANDLER(func) \
diff --git a/drivers/net/fm10k/base/fm10k_type.h b/drivers/net/fm10k/base/fm10k_type.h
index ba0a184..3fc8f13 100644
--- a/drivers/net/fm10k/base/fm10k_type.h
+++ b/drivers/net/fm10k/base/fm10k_type.h
@@ -40,7 +40,6 @@ struct fm10k_hw;
 #include "fm10k_osdep.h"
 #include "fm10k_mbx.h"
 
-#define FM10K_INTEL_VENDOR_ID		0x8086
 #define FM10K_DEV_ID_PF			0x15A4
 #define FM10K_DEV_ID_VF			0x15A5
 #ifdef BOULDER_RAPIDS_HW
@@ -121,28 +120,16 @@ struct fm10k_hw;
 #define FM10K_CTRL_BAR4_ALLOWED			0x00000004
 
 #define FM10K_CTRL_EXT		0x0001
-#define FM10K_CTRL_EXT_NS_DIS			0x00000001
-#define FM10K_CTRL_EXT_RO_DIS			0x00000002
-#define FM10K_CTRL_EXT_SWITCH_LOOPBACK		0x00000004
-#define FM10K_EXVET		0x0002
-#define FM10K_EXVET_ETHERTYPE_MASK		0x000000FF
-#define FM10K_EXVET_TAG_SIZE_SHIFT		16
-#define FM10K_EXVET_AFTER_VLAN			0x00040000
 #define FM10K_GCR		0x0003
-#define FM10K_FACTPS		0x0004
 #define FM10K_GCR_EXT		0x0005
 
 /* Interrupt control registers */
 #define FM10K_EICR		0x0006
-#define FM10K_EICR_PCA_FAULT			0x00000001
-#define FM10K_EICR_THI_FAULT			0x00000004
-#define FM10K_EICR_FUM_FAULT			0x00000020
 #define FM10K_EICR_FAULT_MASK			0x0000003F
 #define FM10K_EICR_MAILBOX			0x00000040
 #define FM10K_EICR_SWITCHREADY			0x00000080
 #define FM10K_EICR_SWITCHNOTREADY		0x00000100
 #define FM10K_EICR_SWITCHINTERRUPT		0x00000200
-#define FM10K_EICR_SRAMERROR			0x00000400
 #define FM10K_EICR_VFLR				0x00000800
 #define FM10K_EICR_MAXHOLDTIME			0x00001000
 #define FM10K_EIMR		0x0007
@@ -196,7 +183,6 @@ struct fm10k_hw;
 #define FM10K_DGLORTDEC_INNERRSS_ENABLE		0x08000000
 #define FM10K_TUNNEL_CFG	0x0040
 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT		16
-#define FM10K_TUNNEL_CFG_GENEVE	0x0041
 #define FM10K_SWPRI_MAP(_n)	((_n) + 0x0050)
 #define FM10K_SWPRI_MAX		16
 #define FM10K_RSSRK(_n, _m)	(((_n) * 0x10) + (_m) + 0x0800)
@@ -217,38 +203,23 @@ struct fm10k_hw;
 #define FM10K_TC_RATE_INTERVAL_4US_GEN1		0x00020000
 #define FM10K_TC_RATE_INTERVAL_4US_GEN2		0x00040000
 #define FM10K_TC_RATE_INTERVAL_4US_GEN3		0x00080000
-#define FM10K_TC_RATE_STATUS	0x20C0
-#define FM10K_PAUSE		0x20C2
 
 /* DMA control registers */
 #define FM10K_DMA_CTRL		0x20C3
 #define FM10K_DMA_CTRL_TX_ENABLE		0x00000001
-#define FM10K_DMA_CTRL_TX_HOST_PENDING		0x00000002
-#define FM10K_DMA_CTRL_TX_DATA			0x00000004
 #define FM10K_DMA_CTRL_TX_ACTIVE		0x00000008
 #define FM10K_DMA_CTRL_RX_ENABLE		0x00000010
-#define FM10K_DMA_CTRL_RX_HOST_PENDING		0x00000020
-#define FM10K_DMA_CTRL_RX_DATA			0x00000040
 #define FM10K_DMA_CTRL_RX_ACTIVE		0x00000080
 #define FM10K_DMA_CTRL_RX_DESC_SIZE		0x00000100
-#define FM10K_DMA_CTRL_MINMSS_SHIFT		9
 #define FM10K_DMA_CTRL_MINMSS_64		0x00008000
-#define FM10K_DMA_CTRL_MAX_HOLD_TIME_SHIFT	23
 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3	0x04800000
 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2	0x04000000
 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1	0x03800000
 #define FM10K_DMA_CTRL_DATAPATH_RESET		0x20000000
-#define FM10K_DMA_CTRL_MAXNUMOFQ_MASK		0xC0000000
 #define FM10K_DMA_CTRL_32_DESC			0x00000000
-#define FM10K_DMA_CTRL_64_DESC			0x40000000
-#define FM10K_DMA_CTRL_128_DESC			0x80000000
 
 #define FM10K_DMA_CTRL2		0x20C4
-#define FM10K_DMA_CTRL2_TX_FRAME_SPACING_SHIFT	5
 #define FM10K_DMA_CTRL2_SWITCH_READY		0x00002000
-#define FM10K_DMA_CTRL2_RX_DESC_READ_PRIO_SHIFT	14
-#define FM10K_DMA_CTRL2_TX_DESC_READ_PRIO_SHIFT	17
-#define FM10K_DMA_CTRL2_TX_DATA_READ_PRIO_SHIFT	20
 
 /* TSO flags configuration
  * First packet contains all flags except for fin and psh
@@ -261,7 +232,6 @@ struct fm10k_hw;
 #define FM10K_DTXTCPFLGH	0x20C6
 
 #define FM10K_TPH_CTRL		0x20C7
-#define FM10K_TPH_CTRL_DISABLE_READ_HINT	0x00000080
 #define FM10K_MRQC(_n)		((_n) + 0x2100)
 #define FM10K_MRQC_TCP_IPV4			0x00000001
 #define FM10K_MRQC_IPV4				0x00000002
@@ -273,7 +243,6 @@ struct fm10k_hw;
 #define FM10K_TQMAP(_n)		((_n) + 0x2800)
 #define FM10K_TQMAP_TABLE_SIZE			2048
 #define FM10K_RQMAP(_n)		((_n) + 0x3000)
-#define FM10K_RQMAP_TABLE_SIZE			2048
 
 /* Hardware Statistics */
 #define FM10K_STATS_TIMEOUT		0x3800
@@ -286,16 +255,11 @@ struct fm10k_hw;
 #define FM10K_STATS_NODESC_DROP		0x3807
 
 /* Timesync registers */
-#define FM10K_RRTIME_CFG	0x3808
-#define FM10K_RRTIME_LIMIT(_n)	((_n) + 0x380C)
-#define FM10K_RRTIME_COUNT(_n)	((_n) + 0x3810)
 #define FM10K_SYSTIME		0x3814
-#define FM10K_SYSTIME0		0x3816
 #define FM10K_SYSTIME_CFG	0x3818
 #define FM10K_SYSTIME_CFG_STEP_MASK		0x0000000F
 
 /* PCIe state registers */
-#define FM10K_PFVFBME(_n)	((_n) + 0x381A)
 #define FM10K_PHYADDR		0x381C
 
 /* Rx ring registers */
@@ -304,8 +268,6 @@ struct fm10k_hw;
 #define FM10K_RDLEN(_n)		((0x40 * (_n)) + 0x4002)
 #define FM10K_TPH_RXCTRL(_n)	((0x40 * (_n)) + 0x4003)
 #define FM10K_TPH_RXCTRL_DESC_TPHEN		0x00000020
-#define FM10K_TPH_RXCTRL_HDR_TPHEN		0x00000040
-#define FM10K_TPH_RXCTRL_DATA_TPHEN		0x00000080
 #define FM10K_TPH_RXCTRL_DESC_RROEN		0x00000200
 #define FM10K_TPH_RXCTRL_DATA_WROEN		0x00002000
 #define FM10K_TPH_RXCTRL_HDR_WROEN		0x00008000
@@ -319,27 +281,10 @@ struct fm10k_hw;
 #define FM10K_RXQCTL_ID_MASK	(FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
 #define FM10K_RXDCTL(_n)	((0x40 * (_n)) + 0x4007)
 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY	0x00000001
-#define FM10K_RXDCTL_WRITE_BACK_IMM		0x00000100
 #define FM10K_RXDCTL_DROP_ON_EMPTY		0x00000200
 #define FM10K_RXINT(_n)		((0x40 * (_n)) + 0x4008)
-#define FM10K_RXINT_TIMER_SHIFT			8
 #define FM10K_SRRCTL(_n)	((0x40 * (_n)) + 0x4009)
 #define FM10K_SRRCTL_BSIZEPKT_SHIFT		8 /* shift _right_ */
-#define FM10K_SRRCTL_BSIZEHDR_SHIFT		2 /* shift _left_ */
-#define FM10K_SRRCTL_BSIZEHDR_MASK		0x00003F00
-#define FM10K_SRRCTL_DESCTYPE_HDR_SPLIT		0x00004000
-#define FM10K_SRRCTL_DESCTYPE_SIZE_SPLIT	0x00008000
-#define FM10K_SRRCTL_PSRTYPE_INNER_TCPHDR	0x00010000
-#define FM10K_SRRCTL_PSRTYPE_INNER_UDPHDR	0x00020000
-#define FM10K_SRRCTL_PSRTYPE_INNER_IPV4HDR	0x00040000
-#define FM10K_SRRCTL_PSRTYPE_INNER_IPV6HDR	0x00080000
-#define FM10K_SRRCTL_PSRTYPE_INNER_L2HDR	0x00100000
-#define FM10K_SRRCTL_PSRTYPE_ENCAPHDR		0x00200000
-#define FM10K_SRRCTL_PSRTYPE_TCPHDR		0x00400000
-#define FM10K_SRRCTL_PSRTYPE_UDPHDR		0x00800000
-#define FM10K_SRRCTL_PSRTYPE_IPV4HDR		0x01000000
-#define FM10K_SRRCTL_PSRTYPE_IPV6HDR		0x02000000
-#define FM10K_SRRCTL_PSRTYPE_L2HDR		0x04000000
 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS		0x40000000
 #define FM10K_SRRCTL_BUFFER_CHAINING_EN		0x80000000
 
@@ -380,7 +325,6 @@ struct fm10k_hw;
 #define FM10K_TXDCTL(_n)	((0x40 * (_n)) + 0x8006)
 #define FM10K_TXDCTL_ENABLE			0x00004000
 #define FM10K_TXDCTL_MAX_TIME_SHIFT		16
-#define FM10K_TXDCTL_PUSH_DESC			0x10000000
 #define FM10K_TXQCTL(_n)	((0x40 * (_n)) + 0x8007)
 #define FM10K_TXQCTL_PF				0x0000003F
 #define FM10K_TXQCTL_VF				0x00000040
@@ -388,13 +332,10 @@ struct fm10k_hw;
 #define FM10K_TXQCTL_PC_SHIFT			7
 #define FM10K_TXQCTL_PC_MASK			0x00000380
 #define FM10K_TXQCTL_TC_SHIFT			10
-#define FM10K_TXQCTL_TC_MASK			0x0000FC00
 #define FM10K_TXQCTL_VID_SHIFT			16
 #define FM10K_TXQCTL_VID_MASK			0x0FFF0000
 #define FM10K_TXQCTL_UNLIMITED_BW		0x10000000
-#define FM10K_TXQCTL_PUSHMODEDIS		0x20000000
 #define FM10K_TXINT(_n)		((0x40 * (_n)) + 0x8008)
-#define FM10K_TXINT_TIMER_SHIFT			8
 
 /* Tx Statistics */
 #define FM10K_QPTC(_n)		((0x40 * (_n)) + 0x8009)
@@ -404,13 +345,7 @@ struct fm10k_hw;
 /* Tx Push registers */
 #define FM10K_TQDLOC(_n)	((0x40 * (_n)) + 0x800C)
 #define FM10K_TQDLOC_BASE_32_DESC		0x08
-#define FM10K_TQDLOC_BASE_64_DESC		0x10
-#define FM10K_TQDLOC_BASE_128_DESC		0x20
 #define FM10K_TQDLOC_SIZE_32_DESC		0x00050000
-#define FM10K_TQDLOC_SIZE_64_DESC		0x00060000
-#define FM10K_TQDLOC_SIZE_128_DESC		0x00070000
-#define FM10K_TQDLOC_SIZE_SHIFT			16
-#define FM10K_TX_DCACHE(_n, _m)	((0x400 * (_n)) + (0x4 * (_m)) + 0x40000)
 
 /* Tx GLORT registers */
 #define FM10K_TX_SGLORT(_n)	((0x40 * (_n)) + 0x800D)
@@ -418,50 +353,27 @@ struct fm10k_hw;
 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE		0x00000001
 
 /* Interrupt moderation and control registers */
-#define FM10K_PBACL(_n)		((_n) + 0x10000)
 #define FM10K_INT_MAP(_n)	((_n) + 0x10080)
 #define FM10K_INT_MAP_TIMER0			0x00000000
 #define FM10K_INT_MAP_TIMER1			0x00000100
 #define FM10K_INT_MAP_IMMEDIATE			0x00000200
 #define FM10K_INT_MAP_DISABLE			0x00000300
-#define FM10K_MSIX_VECTOR_ADDR_LO(_n)	((0x4 * (_n)) + 0x11000)
-#define FM10K_MSIX_VECTOR_ADDR_HI(_n)	((0x4 * (_n)) + 0x11001)
-#define FM10K_MSIX_VECTOR_DATA(_n)	((0x4 * (_n)) + 0x11002)
 #define FM10K_MSIX_VECTOR_MASK(_n)	((0x4 * (_n)) + 0x11003)
 #define FM10K_INT_CTRL		0x12000
 #define FM10K_INT_CTRL_ENABLEMODERATOR		0x00000400
 #define FM10K_ITR(_n)		((_n) + 0x12400)
 #define FM10K_ITR_INTERVAL1_SHIFT		12
-#define FM10K_ITR_TIMER0_EXPIRED		0x01000000
-#define FM10K_ITR_TIMER1_EXPIRED		0x02000000
-#define FM10K_ITR_PENDING0			0x04000000
-#define FM10K_ITR_PENDING1			0x08000000
 #define FM10K_ITR_PENDING2			0x10000000
 #define FM10K_ITR_AUTOMASK			0x20000000
 #define FM10K_ITR_MASK_SET			0x40000000
 #define FM10K_ITR_MASK_CLEAR			0x80000000
 #define FM10K_ITR2(_n)		((0x2 * (_n)) + 0x12800)
-#define FM10K_ITR2_LP(_n)	((0x2 * (_n)) + 0x12801)
 #define FM10K_ITR_REG_COUNT			768
 #define FM10K_ITR_REG_COUNT_PF			256
 
 /* Switch manager interrupt registers */
 #define FM10K_IP		0x13000
-#define FM10K_IP_HOT_RESET			0x00000001
-#define FM10K_IP_DEVICE_STATE_CHANGE		0x00000002
-#define FM10K_IP_MAILBOX			0x00000004
-#define FM10K_IP_VPD_REQUEST			0x00000008
-#define FM10K_IP_SRAMERROR			0x00000010
-#define FM10K_IP_PFLR				0x00000020
-#define FM10K_IP_DATAPATHRESET			0x00000040
-#define FM10K_IP_OUTOFRESET			0x00000080
 #define FM10K_IP_NOTINRESET			0x00000100
-#define FM10K_IP_TIMEOUT			0x00000200
-#define FM10K_IP_VFLR				0x00000400
-#define FM10K_IM		0x13001
-#define FM10K_IB		0x13002
-#define FM10K_SRAM_IP		0x13003
-#define FM10K_SRAM_IM		0x13004
 
 /* VLAN registers */
 #define FM10K_VLAN_TABLE(_n, _m)	((0x80 * (_n)) + (_m) + 0x14000)
@@ -499,12 +411,8 @@ struct fm10k_hw;
 #define FM10K_VFINT_MAP		0x00030
 #define FM10K_VFSYSTIME		0x00040
 #define FM10K_VFITR(_n)		((_n) + 0x00060)
-#define FM10K_VFPBACL(_n)	((_n) + 0x00008)
 
 /* Registers contained in BAR 4 for Switch management */
-#define FM10K_SW_SYSTIME_CFG	0x0224C
-#define FM10K_SW_SYSTIME_CFG_STEP_SHIFT		4
-#define FM10K_SW_SYSTIME_CFG_ADJUST_MASK	0xFF000000
 #define FM10K_SW_SYSTIME_ADJUST	0x0224D
 #define FM10K_SW_SYSTIME_ADJUST_MASK		0x3FFFFFFF
 #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE	0x80000000
@@ -777,8 +685,6 @@ struct fm10k_vf_info {
 #define FM10K_VF_FLAG_CAPABLE(vf_info)	((vf_info)->vf_flags & (u8)0xF)
 #define FM10K_VF_FLAG_ENABLED(vf_info)	((vf_info)->vf_flags >> 4)
 #define FM10K_VF_FLAG_SET_MODE(mode)	((u8)0x10 << (mode))
-#define FM10K_VF_FLAG_ENABLED_MODE_SHIFT	4
-#define FM10K_VF_FLAG_SET_MODE_MASK	((u8)0xF0)
 #define FM10K_VF_FLAG_SET_MODE_NONE \
 	FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
 #define FM10K_VF_FLAG_MULTI_ENABLED \
@@ -849,13 +755,11 @@ struct fm10k_tx_desc_cache {
 #define FM10K_TXD_FLAG_INT	0x01
 #define FM10K_TXD_FLAG_TIME	0x02
 #define FM10K_TXD_FLAG_CSUM	0x04
-#define FM10K_TXD_FLAG_CSUM2	0x08
 #define FM10K_TXD_FLAG_FTAG	0x10
 #define FM10K_TXD_FLAG_RS	0x20
 #define FM10K_TXD_FLAG_LAST	0x40
 #define FM10K_TXD_FLAG_DONE	0x80
 
-#define FM10K_TXD_VLAN_PRI_SHIFT	12
 
 /* These macros are meant to enable optimal placement of the RS and INT
  * bits.  It will point us to the last descriptor in the cache for either the
@@ -864,8 +768,6 @@ struct fm10k_tx_desc_cache {
  * in the FIFO to prevent an unnecessary write.
  */
 #define FM10K_TXD_WB_FIFO_SIZE	4
-#define FM10K_TXD_WB_IDX(idx) \
-	(((idx) - 1) | (FM10K_TXD_WB_FIFO_SIZE - 1))
 
 /* Receive Descriptor - 32B */
 union fm10k_rx_desc {
@@ -910,29 +812,6 @@ enum fm10k_rdesc_rss_type {
 	/* Reserved 0x9 - 0xF */
 };
 
-#define FM10K_RXD_PKTTYPE_MASK		0x03F0
-#define FM10K_RXD_PKTTYPE_MASK_L3	0x0070
-#define FM10K_RXD_PKTTYPE_MASK_L4	0x0380
-#define FM10K_RXD_PKTTYPE_SHIFT		4
-#define FM10K_RXD_PKTTYPE_INNER_MASK_L3	0x1C00
-#define FM10K_RXD_PKTTYPE_INNER_MASK_L4	0xE000
-#define FM10K_RXD_PKTTYPE_INNER_SHIFT	10
-enum fm10k_rdesc_pkt_type {
-	/* L3 type */
-	FM10K_PKTTYPE_OTHER	= 0x00,
-	FM10K_PKTTYPE_IPV4	= 0x01,
-	FM10K_PKTTYPE_IPV4_EX	= 0x02,
-	FM10K_PKTTYPE_IPV6	= 0x03,
-	FM10K_PKTTYPE_IPV6_EX	= 0x04,
-
-	/* L4 type */
-	FM10K_PKTTYPE_TCP	= 0x08,
-	FM10K_PKTTYPE_UDP	= 0x10,
-	FM10K_PKTTYPE_GRE	= 0x18,
-	FM10K_PKTTYPE_VXLAN	= 0x20,
-	FM10K_PKTTYPE_NVGRE	= 0x28,
-	FM10K_PKTTYPE_GENEVE	= 0x30
-};
 
 #define FM10K_RXD_HDR_INFO_XC_MASK	0x0006
 enum fm10k_rxdesc_xc {
@@ -941,20 +820,11 @@ enum fm10k_rxdesc_xc {
 	FM10K_XC_BROADCAST	= 0x6
 };
 
-#define FM10K_RXD_HDR_INFO_LEN_SHIFT	5
-#define FM10K_RXD_HDR_INFO_SPH		0x8000
 
 #define FM10K_RXD_STATUS_DD		0x0001 /* Descriptor done */
 #define FM10K_RXD_STATUS_EOP		0x0002 /* End of packet */
-#define FM10K_RXD_STATUS_VEXT		0x0004 /* A VLAN tag is present */
-#define FM10K_RXD_STATUS_IPCS		0x0008 /* Indicates IPv4 csum */
 #define FM10K_RXD_STATUS_L4CS		0x0010 /* Indicates an L4 csum */
-#define FM10K_RXD_STATUS_IPCS2		0x0020 /* Inner header IPv4 csum */
 #define FM10K_RXD_STATUS_L4CS2		0x0040 /* Inner header L4 csum */
-#define FM10K_RXD_STATUS_IPFRAG_MASK	0x0180 /* Fragment mask */
-#define FM10K_RXD_STATUS_IPFRAG_CSUM	0x0100 /* Fragment w/ CSUM field */
-#define FM10K_RXD_STATUS_VEXT2		0x0200 /* A custom tag is present */
-#define FM10K_RXD_STATUS_HBO		0x0400 /* header buffer overrun */
 #define FM10K_RXD_STATUS_L4E2		0x0800 /* Inner header L4 csum err */
 #define FM10K_RXD_STATUS_IPE2		0x1000 /* Inner header IPv4 csum err */
 #define FM10K_RXD_STATUS_RXE		0x2000 /* Generic Rx error */
@@ -967,8 +837,6 @@ enum fm10k_rxdesc_xc {
 #define FM10K_RXD_ERR_SWITCH_READY	0x0008 /* Link transition mid-packet */
 #define FM10K_RXD_ERR_TOO_BIG		0x0010 /* Pkt too big for single buf */
 
-#define FM10K_RXD_VLAN_ID_MASK		0x0FFF
-#define FM10K_RXD_VLAN_PRI_SHIFT	FM10K_TXD_VLAN_PRI_SHIFT
 
 struct fm10k_ftag {
 	__be16 swpri_type_user;
