From patchwork Wed Jan 27 03:50:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Wang X-Patchwork-Id: 10118 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 44CC39597; Wed, 27 Jan 2016 04:51:28 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 2779B958E for ; Wed, 27 Jan 2016 04:51:26 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP; 26 Jan 2016 19:51:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,353,1449561600"; d="scan'208";a="734904544" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga003.jf.intel.com with ESMTP; 26 Jan 2016 19:51:24 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id u0R3pLRS015834; Wed, 27 Jan 2016 11:51:21 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u0R3pIQm016821; Wed, 27 Jan 2016 11:51:20 +0800 Received: (from xiaowan1@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u0R3pIJd016817; Wed, 27 Jan 2016 11:51:18 +0800 From: Wang Xiao W To: jing.d.chen@intel.com Date: Wed, 27 Jan 2016 11:50:45 +0800 Message-Id: <1453866647-16215-15-git-send-email-xiao.w.wang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1453866647-16215-1-git-send-email-xiao.w.wang@intel.com> References: <1453372561-11431-16-git-send-email-xiao.w.wang@intel.com> <1453866647-16215-1-git-send-email-xiao.w.wang@intel.com> Cc: dev@dpdk.org Subject: [dpdk-dev] [PATCH v2 14/16] fm10k/base: TLV structures must be 4byte aligned, not 1byte aligned X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Per comments from an upstream patch, and looking at how TLV LE_STRUCT code works, we actually want these structures to be 4byte aligned, not 1byte aligned. In practice, 1byte alignment has worked so far because all our structures end up being a multiple of 4. But if a future TLV structure were added that had a u8 or similar sticking on the end things would break. Fix this by using 4byte alignment which will prevent the TLV LE_STRUCT code from breaking. Update the comment explaining that we need 4byte alignment of our structures. Signed-off-by: Wang Xiao W --- drivers/net/fm10k/base/fm10k_pf.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/fm10k/base/fm10k_pf.h b/drivers/net/fm10k/base/fm10k_pf.h index 92e2962..ee8527a 100644 --- a/drivers/net/fm10k/base/fm10k_pf.h +++ b/drivers/net/fm10k/base/fm10k_pf.h @@ -91,14 +91,14 @@ enum fm10k_pf_tlv_attr_id_v1 { #define FM10K_MSG_UPDATE_PVID_PVID_SHIFT 16 #define FM10K_MSG_UPDATE_PVID_PVID_SIZE 16 -/* The following data structures are overlayed specifically to TLV mailbox - * messages, and must not have gaps between their values. They must line up - * correctly to the TLV definition. +/* The following data structures are overlayed directly onto TLV mailbox + * messages, and must not break 4 byte alignment. Ensure the structures line + * up correctly as per their TLV definition. */ #ifdef C99 -#pragma pack(push, 1) +#pragma pack(push, 4) #else -#pragma pack(1) +#pragma pack(4) #endif /* C99 */ struct fm10k_mac_update {