@@ -67,7 +67,7 @@ static struct rte_cryptodev_ops crypto_qat_ops = {
* The set of PCI devices this driver supports
*/
-static struct rte_pci_id pci_id_qat_map[] = {
+static struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_qat_map[] = {
{
.vendor_id = 0x8086,
.device_id = 0x0443,
@@ -17,7 +17,7 @@
* The set of PCI devices this driver supports
*/
#define PCI_VENDOR_ID_BROADCOM 0x14E4
-static struct rte_pci_id pci_id_bnx2x_map[] = {
+static struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_bnx2x_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, CHIP_NUM_57800) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, CHIP_NUM_57711) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, CHIP_NUM_57810) },
@@ -33,7 +33,7 @@ static struct rte_pci_id pci_id_bnx2x_map[] = {
{ .vendor_id = 0, }
};
-static struct rte_pci_id pci_id_bnx2xvf_map[] = {
+static struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_bnx2xvf_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, CHIP_NUM_57800_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, CHIP_NUM_57810_VF) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, CHIP_NUM_57811_VF) },
@@ -68,7 +68,7 @@
* Macros needed to support the PCI Device ID Table ...
*/
#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
- static struct rte_pci_id cxgb4_pci_tbl[] = {
+ static struct rte_pci_id RTE_PCI_ID_UIO_SECTION cxgb4_pci_tbl[] = {
#define CH_PCI_DEVICE_ID_FUNCTION 0x4
#define PCI_VENDOR_ID_CHELSIO 0x1425
@@ -136,7 +136,7 @@ static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
/*
* The set of PCI devices this driver supports
*/
-static const struct rte_pci_id pci_id_em_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_em_map[] = {
#define RTE_PCI_DEV_ID_DECL_EM(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "em_pci_dev_ids.h"
@@ -273,7 +273,7 @@ static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
/*
* The set of PCI devices this driver supports
*/
-static const struct rte_pci_id pci_id_igb_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_igb_map[] = {
#define RTE_PCI_DEV_ID_DECL_IGB(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "igb_pci_dev_ids.h"
@@ -284,7 +284,7 @@ static const struct rte_pci_id pci_id_igb_map[] = {
/*
* The set of PCI devices this driver supports (for 82576&I350 VF)
*/
-static const struct rte_pci_id pci_id_igbvf_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_igbvf_map[] = {
#define RTE_PCI_DEV_ID_DECL_IGBVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "igb_pci_dev_ids.h"
@@ -58,7 +58,7 @@
* The set of PCI devices this driver supports
*/
#define PCI_VENDOR_ID_CISCO 0x1137
-static const struct rte_pci_id pci_id_enic_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_enic_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET_VF) },
{.vendor_id = 0, /* sentinel */},
@@ -2740,7 +2740,7 @@ eth_fm10k_dev_uninit(struct rte_eth_dev *dev)
* The set of PCI devices this driver supports. This driver will enable both PF
* and SRIOV-VF devices.
*/
-static const struct rte_pci_id pci_id_fm10k_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_fm10k_map[] = {
{ RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_PF) },
{ RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_SDI_FM10420_QDA2) },
{ RTE_PCI_DEVICE(FM10K_INTEL_VENDOR_ID, FM10K_DEV_ID_VF) },
@@ -415,7 +415,7 @@ static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
uint16_t queue_id);
-static const struct rte_pci_id pci_id_i40e_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_i40e_map[] = {
{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_A) },
@@ -1116,7 +1116,7 @@ i40evf_get_link_status(struct rte_eth_dev *dev, struct rte_eth_link *link)
return 0;
}
-static const struct rte_pci_id pci_id_i40evf_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_i40evf_map[] = {
{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
{ RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
@@ -378,7 +378,7 @@ static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
/*
* The set of PCI devices this driver supports
*/
-static const struct rte_pci_id pci_id_ixgbe_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_ixgbe_map[] = {
#define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "ixgbe_pci_dev_ids.h"
@@ -390,7 +390,7 @@ static const struct rte_pci_id pci_id_ixgbe_map[] = {
/*
* The set of PCI devices this driver supports (for 82599 VF)
*/
-static const struct rte_pci_id pci_id_ixgbevf_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_ixgbevf_map[] = {
#define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
#include "ixgbe_pci_dev_ids.h"
@@ -2444,7 +2444,7 @@ nfp_net_init(struct rte_eth_dev *eth_dev)
return 0;
}
-static struct rte_pci_id pci_id_nfp_net_map[] = {
+static struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_nfp_net_map[] = {
{
.vendor_id = PCI_VENDOR_ID_NETRONOME,
.device_id = PCI_DEVICE_ID_NFP6000_PF_NIC,
@@ -105,7 +105,7 @@ static int virtio_dev_queue_stats_mapping_set(
/*
* The set of PCI devices this driver supports
*/
-static const struct rte_pci_id pci_id_virtio_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_virtio_map[] = {
{ RTE_PCI_DEVICE(VIRTIO_PCI_VENDORID, VIRTIO_PCI_DEVICEID_MIN) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -100,7 +100,7 @@ static void vmxnet3_process_events(struct vmxnet3_hw *);
*/
#define PCI_VENDOR_ID_VMWARE 0x15AD
#define VMWARE_DEV_ID_VMXNET3 0x07B0
-static const struct rte_pci_id pci_id_vmxnet3_map[] = {
+static const struct rte_pci_id RTE_PCI_ID_UIO_SECTION pci_id_vmxnet3_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWARE_DEV_ID_VMXNET3) },
{ .vendor_id = 0, /* sentinel */ },
};
@@ -131,6 +131,8 @@ struct rte_pci_id {
uint16_t subsystem_device_id; /**< Subsystem device ID or PCI_ANY_ID. */
};
+#define RTE_PCI_ID_UIO_SECTION __attribute__((section("rte_pci_id_uio")))
+
/**
* A structure describing the location of a PCI device.
*/