From patchwork Thu Nov 26 01:35:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Qiu X-Patchwork-Id: 9132 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 50D76C166; Thu, 26 Nov 2015 02:35:21 +0100 (CET) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id B76CAC13C for ; Thu, 26 Nov 2015 02:35:19 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 25 Nov 2015 17:35:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,345,1444719600"; d="scan'208";a="859905118" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 25 Nov 2015 17:35:17 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id tAQ1ZGGo029428; Thu, 26 Nov 2015 09:35:16 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id tAQ1ZDSo021763; Thu, 26 Nov 2015 09:35:15 +0800 Received: (from dayuqiu@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id tAQ1ZCKr021759; Thu, 26 Nov 2015 09:35:12 +0800 From: Michael Qiu To: dev@dpdk.org Date: Thu, 26 Nov 2015 09:35:06 +0800 Message-Id: <1448501706-21718-2-git-send-email-michael.qiu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1448501706-21718-1-git-send-email-michael.qiu@intel.com> References: <1448501706-21718-1-git-send-email-michael.qiu@intel.com> Subject: [dpdk-dev] [PATCH 2/2] Fix compile issue in i686 platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In i686 platform, long is 32bit, so XXX_CYCLECOUNTER_MASK need define as 'ULL' Signed-off-by: Michael Qiu --- drivers/net/e1000/igb_ethdev.c | 2 +- drivers/net/i40e/i40e_ethdev.c | 2 +- drivers/net/ixgbe/ixgbe_ethdev.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index 31452ae..518b6c9 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -78,7 +78,7 @@ #define IGB_8_BIT_MASK UINT8_MAX /* Additional timesync values. */ -#define E1000_CYCLECOUNTER_MASK 0xffffffffffffffff +#define E1000_CYCLECOUNTER_MASK 0xffffffffffffffffULL #define E1000_ETQF_FILTER_1588 3 #define IGB_82576_TSYNC_SHIFT 16 #define E1000_INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 13ab81a..5cd6e88 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -131,7 +131,7 @@ #define I40E_PTP_1GB_INCVAL 0x2000000000ULL #define I40E_PRTTSYN_TSYNENA 0x80000000 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000 -#define I40E_CYCLECOUNTER_MASK 0xffffffffffffffff +#define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL #define I40E_MAX_PERCENT 100 #define I40E_DEFAULT_DCB_APP_NUM 1 diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c index 49f2410..808ac69 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.c +++ b/drivers/net/ixgbe/ixgbe_ethdev.c @@ -136,7 +136,7 @@ #define IXGBE_INCVAL_SHIFT_82599 7 #define IXGBE_INCPER_SHIFT_82599 24 -#define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffff +#define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev); static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);