From patchwork Fri Oct 30 05:27:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cunming Liang X-Patchwork-Id: 8316 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 026908E8B; Fri, 30 Oct 2015 06:28:27 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 262098E7B for ; Fri, 30 Oct 2015 06:28:21 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 29 Oct 2015 22:28:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,217,1444719600"; d="scan'208";a="838585745" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga002.jf.intel.com with ESMTP; 29 Oct 2015 22:28:20 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t9U5SI67023347; Fri, 30 Oct 2015 13:28:18 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t9U5SEjm028919; Fri, 30 Oct 2015 13:28:16 +0800 Received: (from cliang18@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t9U5SEJt028915; Fri, 30 Oct 2015 13:28:14 +0800 From: Cunming Liang To: dev@dpdk.org Date: Fri, 30 Oct 2015 13:27:50 +0800 Message-Id: <1446182873-28814-9-git-send-email-cunming.liang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1446182873-28814-1-git-send-email-cunming.liang@intel.com> References: <1443072831-19065-1-git-send-email-cunming.liang@intel.com> <1446182873-28814-1-git-send-email-cunming.liang@intel.com> Subject: [dpdk-dev] [PATCH v2 08/11] igb: fix rx intr compatible issue with PF mbox X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When igb runs as a PF, mbox interrupt is prerequisite to make VF start normally. And PF sometimes won't 'dev_start', so the mbox interrupt register during 'dev_init' is required. The patch rolls back the interrupt register for mbox,lsc to the 'dev_init'. As UIO doesn't support multiple vector, mbox has to occupy the only one. It adds condition check on 'dev_start', rxq interrupt is not allowed when PF running in IOV mode via UIO. Signed-off-by: Cunming Liang --- drivers/net/e1000/igb_ethdev.c | 44 +++++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c index b3a802f..2494fc8 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -650,6 +650,13 @@ eth_igb_dev_init(struct rte_eth_dev *eth_dev) eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id); + rte_intr_callback_register(&pci_dev->intr_handle, + eth_igb_interrupt_handler, + (void *)eth_dev); + + /* enable uio/vfio intr/eventfd mapping */ + rte_intr_enable(&pci_dev->intr_handle); + /* enable support intr */ igb_intr_enable(eth_dev); @@ -928,13 +935,16 @@ eth_igb_start(struct rte_eth_dev *dev) igb_pf_host_configure(dev); /* check and configure queue intr-vector mapping */ - if (dev->data->dev_conf.intr_conf.rxq != 0) + if (((RTE_ETH_DEV_SRIOV(dev).active && + rte_intr_cap_multiple(intr_handle)) || + !RTE_ETH_DEV_SRIOV(dev).active) && + dev->data->dev_conf.intr_conf.rxq != 0) { intr_vector = dev->data->nb_rx_queues; + if (rte_intr_efd_enable(intr_handle, intr_vector)) + return -1; + } - if (rte_intr_efd_enable(intr_handle, intr_vector)) - return -1; - - if (rte_intr_dp_is_en(intr_handle)) { + if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { intr_handle->intr_vec = rte_zmalloc("intr_vec", dev->data->nb_rx_queues * sizeof(int), 0); @@ -1027,20 +1037,22 @@ eth_igb_start(struct rte_eth_dev *dev) } e1000_setup_link(hw); - /* check if lsc interrupt feature is enabled */ - if (dev->data->dev_conf.intr_conf.lsc != 0) { - if (rte_intr_allow_others(intr_handle)) { - rte_intr_callback_register(intr_handle, - eth_igb_interrupt_handler, - (void *)dev); + if (rte_intr_allow_others(intr_handle)) { + /* check if lsc interrupt is enabled */ + if (dev->data->dev_conf.intr_conf.lsc != 0) eth_igb_lsc_interrupt_setup(dev); - } else + } else { + rte_intr_callback_unregister(intr_handle, + eth_igb_interrupt_handler, + (void *)dev); + if (dev->data->dev_conf.intr_conf.lsc != 0) PMD_INIT_LOG(INFO, "lsc won't enable because of" " no intr multiplex\n"); } /* check if rxq interrupt is enabled */ - if (dev->data->dev_conf.intr_conf.rxq != 0) + if (dev->data->dev_conf.intr_conf.rxq != 0 && + rte_intr_dp_is_en(intr_handle)) eth_igb_rxq_interrupt_setup(dev); /* enable uio/vfio intr/eventfd mapping */ @@ -1133,6 +1145,12 @@ eth_igb_stop(struct rte_eth_dev *dev) } filter_info->twotuple_mask = 0; + if (!rte_intr_allow_others(intr_handle)) + /* resume to the default handler */ + rte_intr_callback_register(intr_handle, + eth_igb_interrupt_handler, + (void *)dev); + /* Clean datapath event and queue/vec mapping */ rte_intr_efd_disable(intr_handle); if (intr_handle->intr_vec != NULL) {