From patchwork Fri Jun 19 19:15:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 5648 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id EAC6DC98C; Fri, 19 Jun 2015 21:15:34 +0200 (CEST) Received: from sclab-apps-2.localdomain (sc-fw1.tilera.com [12.218.212.162]) by dpdk.org (Postfix) with ESMTP id E95F5C930 for ; Fri, 19 Jun 2015 21:15:21 +0200 (CEST) X-CheckPoint: {55846A49-3-A3D4DA0C-C0000002} Received: by sclab-apps-2.localdomain (Postfix, from userid 1318) id 90043220493; Fri, 19 Jun 2015 12:15:10 -0700 (PDT) From: Cyril Chemparathy To: dev@dpdk.org Date: Fri, 19 Jun 2015 12:15:05 -0700 Message-Id: <1434741309-22415-8-git-send-email-cchemparathy@ezchip.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1434741309-22415-1-git-send-email-cchemparathy@ezchip.com> References: <1434741309-22415-1-git-send-email-cchemparathy@ezchip.com> Subject: [dpdk-dev] [PATCH 07/11] mempool: allow config override on element alignment X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On TILE-Gx and TILE-Mx platforms, the buffers fed into the hardware buffer manager require a 128-byte alignment. With this change, we allow configuration based override of the element alignment, and default to RTE_CACHE_LINE_SIZE if left unspecified. Change-Id: I9cd789d92b0bc9c8f44a633de59bb04d45d927a7 Signed-off-by: Cyril Chemparathy --- lib/librte_mempool/rte_mempool.c | 16 +++++++++------- lib/librte_mempool/rte_mempool.h | 6 ++++++ 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/lib/librte_mempool/rte_mempool.c b/lib/librte_mempool/rte_mempool.c index 190cfd9..37823dc 100644 --- a/lib/librte_mempool/rte_mempool.c +++ b/lib/librte_mempool/rte_mempool.c @@ -120,10 +120,10 @@ static unsigned optimize_object_size(unsigned obj_size) nrank = 1; /* process new object size */ - new_obj_size = (obj_size + RTE_CACHE_LINE_MASK) / RTE_CACHE_LINE_SIZE; + new_obj_size = (obj_size + RTE_MEMPOOL_ALIGN_MASK) / RTE_MEMPOOL_ALIGN; while (get_gcd(new_obj_size, nrank * nchan) != 1) new_obj_size++; - return new_obj_size * RTE_CACHE_LINE_SIZE; + return new_obj_size * RTE_MEMPOOL_ALIGN; } static void @@ -265,7 +265,7 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags, #endif if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0) sz->header_size = RTE_ALIGN_CEIL(sz->header_size, - RTE_CACHE_LINE_SIZE); + RTE_MEMPOOL_ALIGN); /* trailer contains the cookie in debug mode */ sz->trailer_size = 0; @@ -279,9 +279,9 @@ rte_mempool_calc_obj_size(uint32_t elt_size, uint32_t flags, if ((flags & MEMPOOL_F_NO_CACHE_ALIGN) == 0) { sz->total_size = sz->header_size + sz->elt_size + sz->trailer_size; - sz->trailer_size += ((RTE_CACHE_LINE_SIZE - - (sz->total_size & RTE_CACHE_LINE_MASK)) & - RTE_CACHE_LINE_MASK); + sz->trailer_size += ((RTE_MEMPOOL_ALIGN - + (sz->total_size & RTE_MEMPOOL_ALIGN_MASK)) & + RTE_MEMPOOL_ALIGN_MASK); } /* @@ -496,7 +496,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size, * cache-aligned */ private_data_size = (private_data_size + - RTE_CACHE_LINE_MASK) & (~RTE_CACHE_LINE_MASK); + RTE_MEMPOOL_ALIGN_MASK) & (~RTE_MEMPOOL_ALIGN_MASK); if (! rte_eal_has_hugepages()) { /* @@ -523,6 +523,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size, * hold mempool header and metadata plus mempool objects. */ mempool_size = MEMPOOL_HEADER_SIZE(mp, pg_num) + private_data_size; + mempool_size = RTE_ALIGN_CEIL(mempool_size, RTE_MEMPOOL_ALIGN); if (vaddr == NULL) mempool_size += (size_t)objsz.total_size * n; @@ -578,6 +579,7 @@ rte_mempool_xmem_create(const char *name, unsigned n, unsigned elt_size, /* calculate address of the first element for continuous mempool. */ obj = (char *)mp + MEMPOOL_HEADER_SIZE(mp, pg_num) + private_data_size; + obj = RTE_PTR_ALIGN_CEIL(obj, RTE_MEMPOOL_ALIGN); /* populate address translation fields. */ mp->pg_num = pg_num; diff --git a/lib/librte_mempool/rte_mempool.h b/lib/librte_mempool/rte_mempool.h index 8be040b..175a793 100644 --- a/lib/librte_mempool/rte_mempool.h +++ b/lib/librte_mempool/rte_mempool.h @@ -139,6 +139,12 @@ struct rte_mempool_objsz { /** Mempool over one chunk of physically continuous memory */ #define MEMPOOL_PG_NUM_DEFAULT 1 +#ifndef RTE_MEMPOOL_ALIGN +#define RTE_MEMPOOL_ALIGN RTE_CACHE_LINE_SIZE +#endif + +#define RTE_MEMPOOL_ALIGN_MASK (RTE_MEMPOOL_ALIGN - 1) + /** * The RTE mempool structure. */