From patchwork Mon Nov 17 04:48:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chao Zhu X-Patchwork-Id: 1309 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 1FFEE8021; Sun, 16 Nov 2014 17:38:01 +0100 (CET) Received: from e28smtp05.in.ibm.com (e28smtp05.in.ibm.com [122.248.162.5]) by dpdk.org (Postfix) with ESMTP id B76A97FB9 for ; Sun, 16 Nov 2014 17:37:37 +0100 (CET) Received: from /spool/local by e28smtp05.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 16 Nov 2014 22:17:49 +0530 Received: from d28dlp02.in.ibm.com (9.184.220.127) by e28smtp05.in.ibm.com (192.168.1.135) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Sun, 16 Nov 2014 22:17:47 +0530 Received: from d28relay05.in.ibm.com (d28relay05.in.ibm.com [9.184.220.62]) by d28dlp02.in.ibm.com (Postfix) with ESMTP id 569053940045 for ; Sun, 16 Nov 2014 22:17:47 +0530 (IST) Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay05.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id sAGGmL4N6947246 for ; Sun, 16 Nov 2014 22:18:21 +0530 Received: from d28av01.in.ibm.com (localhost [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id sAGGlks9031654 for ; Sun, 16 Nov 2014 22:17:46 +0530 Received: from os_controller.crl.ibm.com ([9.186.57.97]) by d28av01.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id sAGGlP3B029091 for ; Sun, 16 Nov 2014 22:17:46 +0530 From: Chao Zhu To: dev@dpdk.org Date: Sun, 16 Nov 2014 23:48:23 -0500 Message-Id: <1416199705-24150-11-git-send-email-chaozhu@linux.vnet.ibm.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com> References: <1416199705-24150-1-git-send-email-chaozhu@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14111616-0017-0000-0000-00000230D130 Subject: [dpdk-dev] [PATCH v2 10/12] Add cache size define for IBM Power Architecture X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" IBM Power architecture has different cache line size (128 bytes) than x86 (64 bytes). This patch defines CACHE_LINE_SIZE to 128 bytes to override the default value 64 bytes to support IBM Power Architecture. Signed-off-by: Chao Zhu --- app/test/test_malloc.c | 8 ++++---- mk/arch/ppc_64/rte.vars.mk | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/app/test/test_malloc.c b/app/test/test_malloc.c index ee34ca3..63e6b32 100644 --- a/app/test/test_malloc.c +++ b/app/test/test_malloc.c @@ -300,9 +300,9 @@ test_big_alloc(void) size_t size =rte_str_to_size(MALLOC_MEMZONE_SIZE)*2; int align = 0; #ifndef RTE_LIBRTE_MALLOC_DEBUG - int overhead = 64 + 64; + int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE; #else - int overhead = 64 + 64 + 64; + int overhead = CACHE_LINE_SIZE + CACHE_LINE_SIZE + CACHE_LINE_SIZE; #endif rte_malloc_get_socket_stats(socket, &pre_stats); @@ -356,9 +356,9 @@ test_multi_alloc_statistics(void) #ifndef RTE_LIBRTE_MALLOC_DEBUG int trailer_size = 0; #else - int trailer_size = 64; + int trailer_size = CACHE_LINE_SIZE; #endif - int overhead = 64 + trailer_size; + int overhead = CACHE_LINE_SIZE + trailer_size; rte_malloc_get_socket_stats(socket, &pre_stats); diff --git a/mk/arch/ppc_64/rte.vars.mk b/mk/arch/ppc_64/rte.vars.mk index 363fcd1..dfdeaea 100644 --- a/mk/arch/ppc_64/rte.vars.mk +++ b/mk/arch/ppc_64/rte.vars.mk @@ -32,7 +32,7 @@ ARCH ?= powerpc CROSS ?= -CPU_CFLAGS ?= -m64 +CPU_CFLAGS ?= -m64 -DCACHE_LINE_SIZE=128 CPU_LDFLAGS ?= CPU_ASFLAGS ?= -felf64