From patchwork Wed Apr 4 03:53:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Lakkireddy X-Patchwork-Id: 37062 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 712621BB5E; Wed, 4 Apr 2018 05:55:12 +0200 (CEST) Received: from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id 0EEED1BB65 for ; Wed, 4 Apr 2018 05:55:10 +0200 (CEST) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id w343t64i014002; Tue, 3 Apr 2018 20:55:07 -0700 From: Rahul Lakkireddy To: dev@dpdk.org Cc: kumaras@chelsio.com, shaguna@chelsio.com, nirranjan@chelsio.com, indranil@chelsio.com Date: Wed, 4 Apr 2018 09:23:37 +0530 Message-Id: <1060bffd76df50e3463ff6ec4179bbce30753b2f.1522768799.git.rahul.lakkireddy@chelsio.com> X-Mailer: git-send-email 2.5.3 In-Reply-To: References: In-Reply-To: References: Subject: [dpdk-dev] [PATCH 3/3] net/cxgbe: update to Rx/Tx offload API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shagun Agrawal Update to new Rx/Tx offload API. Always set CRC stripping during configuration, since it can't be disabled. Signed-off-by: Shagun Agrawal Signed-off-by: Kumar Sanghvi Signed-off-by: Rahul Lakkireddy --- drivers/net/cxgbe/cxgbe_ethdev.c | 87 ++++++++++++++++++++++++++++++++-------- drivers/net/cxgbe/sge.c | 3 +- 2 files changed, 73 insertions(+), 17 deletions(-) diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c index feae01d6a..581a1f33a 100644 --- a/drivers/net/cxgbe/cxgbe_ethdev.c +++ b/drivers/net/cxgbe/cxgbe_ethdev.c @@ -58,6 +58,19 @@ */ #include "t4_pci_id_tbl.h" +#define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\ + DEV_TX_OFFLOAD_IPV4_CKSUM |\ + DEV_TX_OFFLOAD_UDP_CKSUM |\ + DEV_TX_OFFLOAD_TCP_CKSUM |\ + DEV_TX_OFFLOAD_TCP_TSO) + +#define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\ + DEV_RX_OFFLOAD_CRC_STRIP |\ + DEV_RX_OFFLOAD_IPV4_CKSUM |\ + DEV_RX_OFFLOAD_JUMBO_FRAME |\ + DEV_RX_OFFLOAD_UDP_CKSUM |\ + DEV_RX_OFFLOAD_TCP_CKSUM) + uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { @@ -132,16 +145,11 @@ void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, device_info->max_vfs = adapter->params.arch.vfcount; device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ - device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | - DEV_RX_OFFLOAD_IPV4_CKSUM | - DEV_RX_OFFLOAD_UDP_CKSUM | - DEV_RX_OFFLOAD_TCP_CKSUM; + device_info->rx_queue_offload_capa = 0UL; + device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; - device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | - DEV_TX_OFFLOAD_IPV4_CKSUM | - DEV_TX_OFFLOAD_UDP_CKSUM | - DEV_TX_OFFLOAD_TCP_CKSUM | - DEV_TX_OFFLOAD_TCP_TSO; + device_info->tx_queue_offload_capa = 0UL; + device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; device_info->reta_size = pi->rss_size; device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; @@ -229,9 +237,11 @@ int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) /* set to jumbo mode if needed */ if (new_mtu > ETHER_MAX_LEN) - eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; + eth_dev->data->dev_conf.rxmode.offloads |= + DEV_RX_OFFLOAD_JUMBO_FRAME; else - eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; + eth_dev->data->dev_conf.rxmode.offloads &= + ~DEV_RX_OFFLOAD_JUMBO_FRAME; err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, -1, -1, true); @@ -358,9 +368,32 @@ int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) { struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); struct adapter *adapter = pi->adapter; + uint64_t unsupported_offloads, configured_offloads; int err; CXGBE_FUNC_TRACE(); + configured_offloads = eth_dev->data->dev_conf.rxmode.offloads; + if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { + dev_info(adapter, "can't disable hw crc strip\n"); + configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP; + } + + unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS; + if (unsupported_offloads) { + dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. " + "Supported:0x%" PRIx64 "\n", + unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS); + return -ENOTSUP; + } + + configured_offloads = eth_dev->data->dev_conf.txmode.offloads; + unsupported_offloads = configured_offloads & ~CXGBE_TX_OFFLOADS; + if (unsupported_offloads) { + dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. " + "Supported:0x%" PRIx64 "\n", + unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS); + return -ENOTSUP; + } if (!(adapter->flags & FW_QUEUE_BOUND)) { err = setup_sge_fwevtq(adapter); @@ -417,8 +450,15 @@ int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; int err = 0; unsigned int temp_nb_desc; - - RTE_SET_USED(tx_conf); + uint64_t unsupported_offloads; + + unsupported_offloads = tx_conf->offloads & ~CXGBE_TX_OFFLOADS; + if (unsupported_offloads) { + dev_err(adapter, "Tx offloads 0x%" PRIx64 " are not supported. " + "Supported:0x%" PRIx64 "\n", + unsupported_offloads, (uint64_t)CXGBE_TX_OFFLOADS); + return -ENOTSUP; + } dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, @@ -527,8 +567,21 @@ int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, unsigned int temp_nb_desc; struct rte_eth_dev_info dev_info; unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; + uint64_t unsupported_offloads, configured_offloads; - RTE_SET_USED(rx_conf); + configured_offloads = rx_conf->offloads; + if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { + dev_info(adapter, "can't disable hw crc strip\n"); + configured_offloads |= DEV_RX_OFFLOAD_CRC_STRIP; + } + + unsupported_offloads = configured_offloads & ~CXGBE_RX_OFFLOADS; + if (unsupported_offloads) { + dev_err(adapter, "Rx offloads 0x%" PRIx64 " are not supported. " + "Supported:0x%" PRIx64 "\n", + unsupported_offloads, (uint64_t)CXGBE_RX_OFFLOADS); + return -ENOTSUP; + } dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, @@ -576,9 +629,11 @@ int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, /* Set to jumbo mode if necessary */ if (pkt_len > ETHER_MAX_LEN) - eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; + eth_dev->data->dev_conf.rxmode.offloads |= + DEV_RX_OFFLOAD_JUMBO_FRAME; else - eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; + eth_dev->data->dev_conf.rxmode.offloads &= + ~DEV_RX_OFFLOAD_JUMBO_FRAME; err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, &rxq->fl, t4_ethrx_handler, diff --git a/drivers/net/cxgbe/sge.c b/drivers/net/cxgbe/sge.c index 0d866354e..a26712ae1 100644 --- a/drivers/net/cxgbe/sge.c +++ b/drivers/net/cxgbe/sge.c @@ -361,7 +361,8 @@ static unsigned int refill_fl_usembufs(struct adapter *adap, struct sge_fl *q, struct rte_mbuf *buf_bulk[n]; int ret, i; struct rte_pktmbuf_pool_private *mbp_priv; - u8 jumbo_en = rxq->rspq.eth_dev->data->dev_conf.rxmode.jumbo_frame; + u8 jumbo_en = rxq->rspq.eth_dev->data->dev_conf.rxmode.offloads & + DEV_RX_OFFLOAD_JUMBO_FRAME; /* Use jumbo mtu buffers if mbuf data room size can fit jumbo data. */ mbp_priv = rte_mempool_get_priv(rxq->rspq.mb_pool);