[v2,109/148] net/ice/base: implement upper-level PHY control functions

Message ID 0ab981f0168497ee3919566a3e29988ea91ad523.1718204529.git.anatoly.burakov@intel.com (mailing list archive)
State Superseded
Delegated to: Bruce Richardson
Headers
Series Update net/ice base driver to latest upstream snapshot |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Anatoly Burakov June 12, 2024, 3:01 p.m. UTC
  From: Ian Stokes <ian.stokes@intel.com>

Implement upper-level PHY control functions as well as required device specific
defines. These include functions returning basic 56G PHY timing parameters and
definitions for constant parameters.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Ian Stokes <ian.stokes@intel.com>
---
 drivers/net/ice/base/ice_ptp_hw.c | 108 ++++++++++++++++++------------
 drivers/net/ice/base/ice_ptp_hw.h |  96 +++++++++++++++++++++++++-
 drivers/net/ice/base/ice_type.h   |   4 +-
 3 files changed, 162 insertions(+), 46 deletions(-)
  

Patch

diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 7b1f462eee..64c48f5f2a 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -6139,25 +6139,18 @@  int ice_ptp_clear_phy_offset_ready(struct ice_hw *hw)
 int
 ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
 {
-	int err;
-
 	switch (hw->phy_model) {
 	case ICE_PHY_ETH56G:
-		err = ice_read_phy_tstamp_eth56g(hw, block, idx, tstamp);
-		break;
+		return ice_read_phy_tstamp_eth56g(hw, block, idx, tstamp);
 	case ICE_PHY_E830:
 		return ice_read_phy_tstamp_e830(hw, block, idx, tstamp);
 	case ICE_PHY_E810:
-		err = ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
-		break;
+		return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
 	case ICE_PHY_E822:
-		err = ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
-		break;
+		return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
 	default:
-		err = ICE_ERR_NOT_SUPPORTED;
+		return ICE_ERR_NOT_SUPPORTED;
 	}
-
-	return err;
 }
 
 /**
@@ -6173,23 +6166,16 @@  ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
 int
 ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
 {
-	int err;
-
 	switch (hw->phy_model) {
 	case ICE_PHY_ETH56G:
-		err = ice_clear_phy_tstamp_eth56g(hw, block, idx);
-		break;
+		return ice_clear_phy_tstamp_eth56g(hw, block, idx);
 	case ICE_PHY_E810:
-		err = ice_clear_phy_tstamp_e810(hw, block, idx);
-		break;
+		return ice_clear_phy_tstamp_e810(hw, block, idx);
 	case ICE_PHY_E822:
-		err = ice_clear_phy_tstamp_e822(hw, block, idx);
-		break;
+		return ice_clear_phy_tstamp_e822(hw, block, idx);
 	default:
-		err = ICE_ERR_NOT_SUPPORTED;
+		return ICE_ERR_NOT_SUPPORTED;
 	}
-
-	return err;
 }
 
 /**
@@ -6219,7 +6205,6 @@  void ice_ptp_reset_ts_memory(struct ice_hw *hw)
  */
 int ice_ptp_init_phc(struct ice_hw *hw)
 {
-	int err;
 	u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
 
 	/* Enable source clocks */
@@ -6230,19 +6215,14 @@  int ice_ptp_init_phc(struct ice_hw *hw)
 
 	switch (hw->phy_model) {
 	case ICE_PHY_ETH56G:
-		err = ice_ptp_init_phc_eth56g(hw);
-		break;
+		return ice_ptp_init_phc_eth56g(hw);
 	case ICE_PHY_E810:
-		err = ice_ptp_init_phc_e810(hw);
-		break;
+		return ice_ptp_init_phc_e810(hw);
 	case ICE_PHY_E822:
-		err = ice_ptp_init_phc_e822(hw);
-		break;
+		return ice_ptp_init_phc_e822(hw);
 	default:
-		err = ICE_ERR_NOT_SUPPORTED;
+		return ICE_ERR_NOT_SUPPORTED;
 	}
-
-	return err;
 }
 
 /**
@@ -6258,26 +6238,66 @@  int ice_ptp_init_phc(struct ice_hw *hw)
  */
 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
 {
-	int err;
-
 	switch (hw->phy_model) {
 	case ICE_PHY_ETH56G:
-		err = ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
-							 tstamp_ready);
-		break;
+		return ice_get_phy_tx_tstamp_ready_eth56g(hw, block,
+							  tstamp_ready);
 	case ICE_PHY_E810:
-		err = ice_get_phy_tx_tstamp_ready_e810(hw, block,
-						       tstamp_ready);
-		break;
+		return ice_get_phy_tx_tstamp_ready_e810(hw, block,
+							tstamp_ready);
 	case ICE_PHY_E822:
-		err = ice_get_phy_tx_tstamp_ready_e822(hw, block,
-						       tstamp_ready);
+		return ice_get_phy_tx_tstamp_ready_e822(hw, block,
+							tstamp_ready);
 		break;
 	default:
-		err = ICE_ERR_NOT_SUPPORTED;
+		return ICE_ERR_NOT_SUPPORTED;
+	}
+}
+
+/**
+ * ice_ptp_read_port_capture - Read a port's local time capture
+ * @hw: pointer to HW struct
+ * @port: Port number to read
+ * @tx_ts: on return, the Tx port time capture
+ * @rx_ts: on return, the Rx port time capture
+ *
+ * Read the port's Tx and Rx local time capture values.
+ */
+int
+ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts,
+			  u64 *rx_ts)
+{
+	switch (hw->phy_model) {
+	case ICE_PHY_ETH56G:
+		return ice_ptp_read_port_capture_eth56g(hw, port,
+							tx_ts, rx_ts);
+	case ICE_PHY_E822:
+		return ice_ptp_read_port_capture_e822(hw, port,
+						      tx_ts, rx_ts);
+	default:
+		return ICE_ERR_NOT_SUPPORTED;
 	}
+}
 
-	return err;
+/**
+ * ice_ptp_read_phy_incval - Read a PHY port's current incval
+ * @hw: pointer to the HW struct
+ * @port: the port to read
+ * @incval: on return, the time_clk_cyc incval for this port
+ *
+ * Read the time_clk_cyc increment value for a given PHY port.
+ */
+int
+ice_ptp_read_phy_incval(struct ice_hw *hw, u8 port, u64 *incval)
+{
+	switch (hw->phy_model) {
+	case ICE_PHY_ETH56G:
+		return ice_ptp_read_phy_incval_eth56g(hw, port, incval);
+	case ICE_PHY_E822:
+		return ice_ptp_read_phy_incval_e822(hw, port, incval);
+	default:
+		return ICE_ERR_NOT_SUPPORTED;
+	}
 }
 
 /**
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index e11b47c528..8b102dc0e3 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -41,6 +41,14 @@  enum ice_ptp_fec_mode {
 	ICE_PTP_FEC_MODE_RS_FEC
 };
 
+/* Main timer mode */
+enum ice_src_tmr_mode {
+	ICE_SRC_TMR_MODE_NANOSECONDS,
+	ICE_SRC_TMR_MODE_LOCKED,
+
+	NUM_ICE_SRC_TMR_MODE
+};
+
 /**
  * struct ice_time_ref_info_e822
  * @pll_freq: Frequency of PLL that drives timer ticks in Hz
@@ -123,7 +131,10 @@  extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
  * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
  */
-#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
+
+#define ICE_E810_PLL_FREQ		812500000
+#define ICE_PTP_NOMINAL_INCVAL_E810	0x13b13b13bULL
+#define E810_OUT_PROP_DELAY_NS 1
 
 /* Device agnostic functions */
 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
@@ -156,6 +167,8 @@  int
 ice_ptp_read_phy_incval(struct ice_hw *hw, u8 port, u64 *incval);
 
 /* E822 family functions */
+#define LOCKED_INCVAL_E822 0x100000000ULL
+
 int
 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
 int
@@ -309,8 +322,89 @@  ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass);
 int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
 int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
 
+#define ICE_ETH56G_PLL_FREQ		800000000
+#define ICE_ETH56G_NOMINAL_INCVAL	0x140000000ULL
+
+static inline u64 ice_eth56g_pps_delay(void)
+{
+	return 0;
+}
+
 void ice_ptp_init_phy_model(struct ice_hw *hw);
 
+/**
+ * ice_ptp_get_pll_freq - Get PLL frequency
+ * @hw: Board private structure
+ */
+static inline u64
+ice_ptp_get_pll_freq(struct ice_hw *hw)
+{
+	switch (hw->phy_model) {
+	case ICE_PHY_ETH56G:
+		return ICE_ETH56G_PLL_FREQ;
+	case ICE_PHY_E810:
+		return ICE_E810_PLL_FREQ;
+	case ICE_PHY_E822:
+		return ice_e822_pll_freq(ice_e822_time_ref(hw));
+	default:
+		return 0;
+	}
+}
+
+static inline u64
+ice_prop_delay(struct ice_hw *hw)
+{
+	switch (hw->phy_model) {
+	case ICE_PHY_ETH56G:
+		return ice_eth56g_pps_delay();
+	case ICE_PHY_E810:
+		return E810_OUT_PROP_DELAY_NS;
+	case ICE_PHY_E822:
+		return ice_e822_pps_delay(ice_e822_time_ref(hw));
+	default:
+		return 0;
+	}
+}
+
+static inline enum ice_time_ref_freq
+ice_time_ref(struct ice_hw *hw)
+{
+	switch (hw->phy_model) {
+	case ICE_PHY_ETH56G:
+		return ICE_TIME_REF_FREQ_125_000;
+	case ICE_PHY_E810:
+	case ICE_PHY_E822:
+		return ice_e822_time_ref(hw);
+	default:
+		return ICE_TIME_REF_FREQ_INVALID;
+	}
+}
+
+static inline u64
+ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode)
+{
+	switch (hw->phy_model) {
+	case ICE_PHY_ETH56G:
+		if (src_tmr_mode == ICE_SRC_TMR_MODE_NANOSECONDS)
+			return ICE_ETH56G_NOMINAL_INCVAL;
+		else
+			return LOCKED_INCVAL_E822;
+	case ICE_PHY_E830:
+	case ICE_PHY_E810:
+		return ICE_PTP_NOMINAL_INCVAL_E810;
+	case ICE_PHY_E822:
+		if (src_tmr_mode == ICE_SRC_TMR_MODE_NANOSECONDS &&
+		    ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
+			return ice_e822_nominal_incval(ice_e822_time_ref(hw));
+		else
+			return LOCKED_INCVAL_E822;
+
+		break;
+	default:
+		return 0;
+	}
+}
+
 #define PFTSYN_SEM_BYTES	4
 
 #define ICE_PTP_CLOCK_INDEX_0	0x00
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index a00edc0ea6..c74da348a3 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -750,7 +750,9 @@  enum ice_time_ref_freq {
 	ICE_TIME_REF_FREQ_156_250	= 4,
 	ICE_TIME_REF_FREQ_245_760	= 5,
 
-	NUM_ICE_TIME_REF_FREQ
+	NUM_ICE_TIME_REF_FREQ,
+
+	ICE_TIME_REF_FREQ_INVALID	= -1,
 };
 
 /* Clock source specification */