From patchwork Thu Sep 28 08:44:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 201 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 55C1B4265E; Thu, 28 Sep 2023 10:45:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 43E2C40273; Thu, 28 Sep 2023 10:45:08 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id CDBBB40150 for ; Thu, 28 Sep 2023 10:45:06 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695890706; x=1727426706; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Hht+5D2QmElt/RnBacHvUaeCB8ZyE0oECz6ZXKSBBQs=; b=BRPva4QPgIhpUQesQqUjiuq7+J2z8vksnNeZKaOvQV5jQ8Ffm2Z52bu4 lGtavcmCwShcPc5FwuIhctQIORRI0+IkX1dVXETZEIPKb3q5GUJMfPj9o C5ZRhRI2M+YXPJRNfu3XU5Qo7y0ExYZ54OUcTLLrES5Wp52s02IR9F+WF jtH5+e6Idx+SuogFvqoucSo9051lVgOShwKZgnUg1bIGCZSVg5uquFoJN 3+b6vOP72Ga9E5qMWrmIklO04sVTiRjGqbJMKYyyvyE+HlmUg2ivtnWBX YiDez4wNsFbaWZ0hDJaMy4mRAnoe9ADbUbVHzzY+MO5hlncrwfcoO+IHh A==; X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="468299453" X-IronPort-AV: E=Sophos;i="6.03,183,1694761200"; d="scan'208";a="468299453" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2023 01:45:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="784622163" X-IronPort-AV: E=Sophos;i="6.03,183,1694761200"; d="scan'208";a="784622163" Received: from dpdk-wenjing-02.sh.intel.com ([10.67.119.3]) by orsmga001.jf.intel.com with ESMTP; 28 Sep 2023 01:45:02 -0700 From: yuying.zhang@intel.com To: yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v9 0/9] add rte flow support for cpfl Date: Thu, 28 Sep 2023 08:44:49 +0000 Message-Id: <20230928084458.2333663-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230927125416.2308974-1-yuying.zhang@intel.com> References: <20230927125416.2308974-1-yuying.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Yuying Zhang This patchset add rte flow support for cpfl driver. It depends on the following patch set: http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-beilei.xing@intel.com/ Wenjing Qiao (2): net/cpfl: add json parser for rte flow pattern rules net/cpfl: build action mapping rules from JSON Yuying Zhang (7): net/cpfl: set up rte flow skeleton net/cpfl: set up control path net/cpfl: add FXP low level implementation net/cpfl: add fxp rule module net/cpfl: add fxp flow engine net/cpfl: add flow support for representor net/cpfl: add support of to represented port action Acked-by: Qi Zhang --- v9: * refine rx queue message process function v8: * fix compile issues * refine document and separate patch with different features v7: * refine commit log * fix compile issues v6: * use existed jansson instead of json-c library. * refine "add FXP low level implementation" V5: * Add input validation for some functions. doc/guides/nics/cpfl.rst | 52 + doc/guides/rel_notes/release_23_11.rst | 1 + drivers/net/cpfl/cpfl_actions.h | 858 +++++++++++ drivers/net/cpfl/cpfl_controlq.c | 801 ++++++++++ drivers/net/cpfl/cpfl_controlq.h | 75 + drivers/net/cpfl/cpfl_ethdev.c | 392 ++++- drivers/net/cpfl/cpfl_ethdev.h | 128 ++ drivers/net/cpfl/cpfl_flow.c | 339 +++++ drivers/net/cpfl/cpfl_flow.h | 85 ++ drivers/net/cpfl/cpfl_flow_engine_fxp.c | 667 ++++++++ drivers/net/cpfl/cpfl_flow_parser.c | 1839 +++++++++++++++++++++++ drivers/net/cpfl/cpfl_flow_parser.h | 267 ++++ drivers/net/cpfl/cpfl_fxp_rule.c | 263 ++++ drivers/net/cpfl/cpfl_fxp_rule.h | 68 + drivers/net/cpfl/cpfl_representor.c | 29 + drivers/net/cpfl/cpfl_rules.c | 127 ++ drivers/net/cpfl/cpfl_rules.h | 306 ++++ drivers/net/cpfl/cpfl_vchnl.c | 144 ++ drivers/net/cpfl/meson.build | 12 + 19 files changed, 6452 insertions(+), 1 deletion(-) create mode 100644 drivers/net/cpfl/cpfl_actions.h create mode 100644 drivers/net/cpfl/cpfl_controlq.c create mode 100644 drivers/net/cpfl/cpfl_controlq.h create mode 100644 drivers/net/cpfl/cpfl_flow.c create mode 100644 drivers/net/cpfl/cpfl_flow.h create mode 100644 drivers/net/cpfl/cpfl_flow_engine_fxp.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.h create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.h create mode 100644 drivers/net/cpfl/cpfl_rules.c create mode 100644 drivers/net/cpfl/cpfl_rules.h