From patchwork Tue Sep 26 11:29:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 184 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8BB764263C; Tue, 26 Sep 2023 05:09:24 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5DD7940271; Tue, 26 Sep 2023 05:09:24 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id DE0C84026F for ; Tue, 26 Sep 2023 05:09:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695697762; x=1727233762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Oa46nHETkQ+LYP8X+L6yH2Ryc9SoUT4NCiVnhAYs8Ng=; b=VwEWrUFmmOm/dYGwh+322puIC00iRpNu1zhPNe0ohmOwSRwWVBRtVQzL d4oeMzzIiYIAsEGOlRFVtrZfc0XS7igF2ODWUKtDpOcl1abrovSRAZtZ8 //Uuwn1MpZ4sCaGwZa8rwYnhkr8WMknuzWE/kTSxxfPNOG/1DdkcMLNBa AgLfGpaovdQRgg1QVl7BPloPUXQJz6YmFZhvcJw4CfsC0+iAdp/mUtmSg VHAeoRQrBICgWug4EBQ04PUIrjuvr8oXAWNrUHw9VL2aO2Fkez+1F1ZBa yOZ8ZmER9Io51E5mRRDC9RehuukQeXz5TtnjLuD/xcmzd922tk8FFmPNa A==; X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="384246940" X-IronPort-AV: E=Sophos;i="6.03,176,1694761200"; d="scan'208";a="384246940" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2023 20:09:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="818878492" X-IronPort-AV: E=Sophos;i="6.03,176,1694761200"; d="scan'208";a="818878492" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.37]) by fmsmga004.fm.intel.com with ESMTP; 25 Sep 2023 20:09:18 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: zhichaox.zeng@intel.com, dev@dpdk.org, Qi Zhang Subject: [PATCH v5 0/5] net/ice: refactor rte_flow Date: Tue, 26 Sep 2023 07:29:26 -0400 Message-Id: <20230926112931.4191107-1-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230814202616.3346652-1-qi.z.zhang@intel.com> References: <20230814202616.3346652-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 1. remove pipeline mode 2. apply group to hardware pipeline stage static mapping 3. add genenic flow document v5: - remove incorrect group attr check in ice_flow_valid_attr v4: - fix error handling when target engine was disabled. v3: - fix the issue when acl=off on dcf mode - refine the disabled engine handling - unified the supported pattern variable name - add document v2: - fix segment fault when an uninitialized engine has been selected. Qi Zhang (5): net/ice: remove pipeline mode net/ice: refine flow engine disabling net/ice: map group to pipeline stage net/ice: refine supported flow pattern name doc: add generic flow doc for ice PMD doc/guides/nics/ice.rst | 64 ++++-- drivers/net/ice/ice_acl_filter.c | 22 +- drivers/net/ice/ice_dcf_parent.c | 3 + drivers/net/ice/ice_ethdev.c | 9 +- drivers/net/ice/ice_ethdev.h | 4 - drivers/net/ice/ice_fdir_filter.c | 30 +-- drivers/net/ice/ice_generic_flow.c | 302 +++++++--------------------- drivers/net/ice/ice_generic_flow.h | 15 +- drivers/net/ice/ice_hash.c | 19 +- drivers/net/ice/ice_switch_filter.c | 133 +----------- 10 files changed, 157 insertions(+), 444 deletions(-)