From patchwork Tue Sep 12 10:00:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qi Zhang X-Patchwork-Id: 128 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8ABD842575; Tue, 12 Sep 2023 03:40:40 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0F8BF40272; Tue, 12 Sep 2023 03:40:40 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id E9A6340223 for ; Tue, 12 Sep 2023 03:40:38 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694482839; x=1726018839; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UZkA0r83HTDI6W3T5uiSUFg5uwGBMMiJfnKgLF6MEgE=; b=RjVg5rD+QQnuYbQOYTRPTfY23f7fQizqU0QPdEcase9uM4USEJCkuriC 8RneJUvaPLFVPAHsNvxTd51Yaxdn2uCrqB/taFWVZkzgyNw3RJFKav/43 xqznrLn81Lyax65iNWknriXxED0WCgeXbfmfaxm5xmHyllK5Gf9QfoBXO lF3m4GhziOoBZQwpKvrm24gkQaVVnsyHZQXGlucK73V64u00pnaruBQy/ yYZ2DLm1umSG9rRIE5CfZfXzbIRDrbGui61JbTCJ43k0OmdlI9Fta69yK Gvsb2k4DjJZqUk1eAmDFD4TIhX2TRVCz/aGx/2btFchykjzmafF51Uudf w==; X-IronPort-AV: E=McAfee;i="6600,9927,10830"; a="382063130" X-IronPort-AV: E=Sophos;i="6.02,244,1688454000"; d="scan'208";a="382063130" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2023 18:40:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10830"; a="867168234" X-IronPort-AV: E=Sophos;i="6.02,244,1688454000"; d="scan'208";a="867168234" Received: from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.37]) by orsmga004.jf.intel.com with ESMTP; 11 Sep 2023 18:40:35 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: zhichaox.zeng@intel.com, dev@dpdk.org, Qi Zhang Subject: [PATCH v3 0/5] refactor rte_flow Date: Tue, 12 Sep 2023 06:00:36 -0400 Message-Id: <20230912100041.3697012-1-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230814202616.3346652-1-qi.z.zhang@intel.com> References: <20230814202616.3346652-1-qi.z.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org 1. remove pipeline mode 2. apply group to hardware pipeline stage static mapping 3. add genenic flow document v3: - fix the issue when acl=off on dcf mode - refine the disabled engine handling - unified the supported pattern variable name - add document v2: - fix segment fault when an unintialized engine has been selected. Qi Zhang (5): net/ice: remove pipeline mode net/ice: refine flow engine disabling net/ice: map group to pipeline stage net/ice: refine supported flow pattern name doc: add generic flow doc for ice PMD doc/guides/nics/ice.rst | 64 +++++-- drivers/net/ice/ice_acl_filter.c | 22 +-- drivers/net/ice/ice_dcf_parent.c | 3 + drivers/net/ice/ice_ethdev.c | 9 +- drivers/net/ice/ice_ethdev.h | 4 - drivers/net/ice/ice_fdir_filter.c | 30 +-- drivers/net/ice/ice_generic_flow.c | 284 +++++++--------------------- drivers/net/ice/ice_generic_flow.h | 15 +- drivers/net/ice/ice_hash.c | 19 +- drivers/net/ice/ice_switch_filter.c | 133 +------------ 10 files changed, 146 insertions(+), 437 deletions(-)