Message ID | 20230908160552.148060-1-yuying.zhang@intel.com (mailing list archive) |
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Headers |
Return-Path: <dev-bounces@dpdk.org> X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7F76D42338; Mon, 9 Oct 2023 10:02:12 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 18043402A3; Mon, 9 Oct 2023 10:02:12 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 8E33B4021F for <dev@dpdk.org>; Mon, 9 Oct 2023 10:02:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696838530; x=1728374530; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=x2r8k8O5ZxxUO8KRoowIGUB635LKu+95ViS0nAyjofU=; b=lh7PshYzzChS75yTdVyryA+LsGZaV9QnWN9JYZpWdcT08+zmBtwJ8WYy JXIiyqgw2co2pjaoeyt5eUiCWbqs5OgYGRTh4+Vh1SzS7JUz4w0cT8YCm zSLNhUyVJwQY/JJmeDVl2al7t9ROgh9SdRqm5o9P+fgnhr4Sr9qAJ5B/D S5Kw4gkWKxFhlI7VLFH6mDmRvZcXlopcXPu/lO5GWkBlUyJ9cKJPO2dNT d1e1vMBFGpAFANQHEPSnHOJfhJHQGOu2amtV7+/sXu+lXkTERMtpjLxDI T7+viwLGXMC7/ibKoSygsR1/2KWYnvzPl5V7cJCoao3gPvJ+dRzicdurZ w==; X-IronPort-AV: E=McAfee;i="6600,9927,10857"; a="369155037" X-IronPort-AV: E=Sophos;i="6.03,209,1694761200"; d="scan'208";a="369155037" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2023 01:02:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10857"; a="926675788" X-IronPort-AV: E=Sophos;i="6.03,209,1694761200"; d="scan'208";a="926675788" Received: from dpdk-pengyuan-mev.sh.intel.com ([10.67.119.132]) by orsmga005.jf.intel.com with ESMTP; 09 Oct 2023 01:02:07 -0700 From: "Zhang, Yuying" <yuying.zhang@intel.com> To: yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v10 0/9] add rte flow support for cpfl Date: Fri, 8 Sep 2023 16:05:43 +0000 Message-Id: <20230908160552.148060-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928084458.2333663-1-yuying.zhang@intel.com> References: <20230928084458.2333663-1-yuying.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org |
Series |
add rte flow support for cpfl
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Message
Zhang, Yuying
Sept. 8, 2023, 4:05 p.m. UTC
From: Yuying Zhang <yuying.zhang@intel.com>
This patchset add rte flow support for cpfl driver.
It depends on the following patch set:
http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-beilei.xing@intel.com/
Wenjing Qiao (2):
net/cpfl: parse flow offloading hint from JSON
net/cpfl: build action mapping rules from JSON
Yuying Zhang (7):
net/cpfl: set up flow offloading skeleton
net/cpfl: set up control path
net/cpfl: add FXP low level implementation
net/cpfl: implement FXP rule creation and destroying
net/cpfl: adapt FXP to flow engine
net/cpfl: support flow ops on representor
net/cpfl: support represented port action
---
v10:
* fix ci build issue
v9:
* refine rx queue message process function
v8:
* fix compile issues
* refine document and separate patch with different features
v7:
* refine commit log
* fix compile issues
v6:
* use existed jansson instead of json-c library
* refine "add FXP low level implementation"
V5:
* Add input validation for some functions
doc/guides/nics/cpfl.rst | 52 +
doc/guides/rel_notes/release_23_11.rst | 1 +
drivers/net/cpfl/cpfl_actions.h | 858 +++++++++++
drivers/net/cpfl/cpfl_controlq.c | 801 ++++++++++
drivers/net/cpfl/cpfl_controlq.h | 75 +
drivers/net/cpfl/cpfl_ethdev.c | 392 ++++-
drivers/net/cpfl/cpfl_ethdev.h | 128 ++
drivers/net/cpfl/cpfl_flow.c | 339 +++++
drivers/net/cpfl/cpfl_flow.h | 85 ++
drivers/net/cpfl/cpfl_flow_engine_fxp.c | 666 ++++++++
drivers/net/cpfl/cpfl_flow_parser.c | 1835 +++++++++++++++++++++++
drivers/net/cpfl/cpfl_flow_parser.h | 268 ++++
drivers/net/cpfl/cpfl_fxp_rule.c | 263 ++++
drivers/net/cpfl/cpfl_fxp_rule.h | 68 +
drivers/net/cpfl/cpfl_representor.c | 29 +
drivers/net/cpfl/cpfl_rules.c | 127 ++
drivers/net/cpfl/cpfl_rules.h | 306 ++++
drivers/net/cpfl/cpfl_vchnl.c | 144 ++
drivers/net/cpfl/meson.build | 12 +
19 files changed, 6448 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/cpfl/cpfl_actions.h
create mode 100644 drivers/net/cpfl/cpfl_controlq.c
create mode 100644 drivers/net/cpfl/cpfl_controlq.h
create mode 100644 drivers/net/cpfl/cpfl_flow.c
create mode 100644 drivers/net/cpfl/cpfl_flow.h
create mode 100644 drivers/net/cpfl/cpfl_flow_engine_fxp.c
create mode 100644 drivers/net/cpfl/cpfl_flow_parser.c
create mode 100644 drivers/net/cpfl/cpfl_flow_parser.h
create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c
create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.h
create mode 100644 drivers/net/cpfl/cpfl_rules.c
create mode 100644 drivers/net/cpfl/cpfl_rules.h