From patchwork Fri Sep 1 11:31:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 107 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 57C5A4221F; Fri, 1 Sep 2023 13:09:36 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D94BA402A0; Fri, 1 Sep 2023 13:09:35 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 43B0C40285 for ; Fri, 1 Sep 2023 13:09:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1693566574; x=1725102574; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Zf5BsV/lO9fXXW7fJtUHqYEy4qFCzQwVa4p4qWd09Qg=; b=CAOp2McLbD2ViRT5UBgBaltF+j+NZDjOSX4MN0/jxxcljzmp9aknUI9h goJJQOrnbAjqxj/xnppE5nsWNalMFIbrt7EVzMuxa4XFRB6Gpdzx4M/6V PX+i/ydAyUJw1zM4hDJM3c1k+wT0KvufXotZPjzIQWsJS6yJS3/HVUv+q SR+eyxpvb3QBfNZPjCRmw+/x2VuXL1AFWq6kPemg1g1/ciiXpyZ/6wTvZ l5/kQmVl3Nsd/Pw6SxypxScOO9DohKP97XFOhdNKfepTdculqf6ARLgMM G3XmBIt7NbWKQ/ieg/EbYoDQN1ll0psh/5SqwG4UGQj+p3UHMlip/6/gR w==; X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="356511006" X-IronPort-AV: E=Sophos;i="6.02,219,1688454000"; d="scan'208";a="356511006" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2023 04:09:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10819"; a="854670953" X-IronPort-AV: E=Sophos;i="6.02,219,1688454000"; d="scan'208";a="854670953" Received: from dpdk-yuyingzh-icelake.sh.intel.com ([10.67.116.226]) by fmsmga002.fm.intel.com with ESMTP; 01 Sep 2023 04:09:25 -0700 From: Yuying Zhang To: dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Cc: Yuying Zhang Subject: [PATCH v2 0/8] add rte flow support for cpfl Date: Fri, 1 Sep 2023 11:31:50 +0000 Message-Id: <20230901113158.1654044-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230812075506.361769-1-yuying.zhang@intel.com> References: <20230812075506.361769-1-yuying.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patchset add rte_flow support for cpfl driver. It depends on the following patch set: http://patchwork.dpdk.org/project/dpdk/cover/20230816150541.144532-1-beilei.xing@intel.com/ Wenjing Qiao (4): net/cpfl: parse flow parser file in devargs net/cpfl: add flow json parser net/cpfl: add FXP low level implementation net/cpfl: setup ctrl path Yuying Zhang (4): net/cpfl: set up rte flow skeleton net/cpfl: add fxp rule module net/cpfl: add fxp flow engine net/cpfl: add flow support for representor doc/guides/nics/cpfl.rst | 45 + doc/guides/rel_notes/release_23_11.rst | 1 + drivers/net/cpfl/cpfl_actions.h | 858 +++++++++++ drivers/net/cpfl/cpfl_controlq.c | 803 ++++++++++ drivers/net/cpfl/cpfl_controlq.h | 75 + drivers/net/cpfl/cpfl_ethdev.c | 390 ++++- drivers/net/cpfl/cpfl_ethdev.h | 109 ++ drivers/net/cpfl/cpfl_flow.c | 339 +++++ drivers/net/cpfl/cpfl_flow.h | 85 ++ drivers/net/cpfl/cpfl_flow_engine_fxp.c | 603 ++++++++ drivers/net/cpfl/cpfl_flow_parser.c | 1769 +++++++++++++++++++++++ drivers/net/cpfl/cpfl_flow_parser.h | 220 +++ drivers/net/cpfl/cpfl_fxp_rule.c | 297 ++++ drivers/net/cpfl/cpfl_fxp_rule.h | 68 + drivers/net/cpfl/cpfl_representor.c | 29 + drivers/net/cpfl/cpfl_rules.c | 126 ++ drivers/net/cpfl/cpfl_rules.h | 306 ++++ drivers/net/cpfl/cpfl_vchnl.c | 144 ++ drivers/net/cpfl/meson.build | 14 + 19 files changed, 6280 insertions(+), 1 deletion(-) create mode 100644 drivers/net/cpfl/cpfl_actions.h create mode 100644 drivers/net/cpfl/cpfl_controlq.c create mode 100644 drivers/net/cpfl/cpfl_controlq.h create mode 100644 drivers/net/cpfl/cpfl_flow.c create mode 100644 drivers/net/cpfl/cpfl_flow.h create mode 100644 drivers/net/cpfl/cpfl_flow_engine_fxp.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.h create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.h create mode 100644 drivers/net/cpfl/cpfl_rules.c create mode 100644 drivers/net/cpfl/cpfl_rules.h