From patchwork Tue Aug 22 01:02:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Yuying" X-Patchwork-Id: 168 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A65D42608; Thu, 21 Sep 2023 18:58:53 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BD55F4013F; Thu, 21 Sep 2023 18:58:52 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id CB42E400D7 for ; Thu, 21 Sep 2023 18:58:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695315532; x=1726851532; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=ZCLJ4B26gHsLkzIswn9S03iHbv/Y9vp++1mOGWKyuCI=; b=Jlw8rG7LTX8J6lhKIM/dwUHHFxEa1e8JcjITqvxnFP85dWoAtBhZNivs iXNXx/MuAEdqhsxqoiSJNo5w4w4ziRF3cXhjRYolMcv7NXhZRD1vYPl6J RXhXVZKC7n8s2nfY678MCk/mtw/oR7khwovEQqEWzw+/SeLq+k2I6N1JF Mg9PxeXtHamj+IaZ7v8/2lDYimjocTFeBw6AdMr+ozHl8aTQDfB4/wX1H pyukVX0cmwKrtWJhjRzuV6FQ0WW2qIHEMaZ4a/2pP2kDMG8VBtgYwIw84 BVz36Df9GlZUj5MQbQvfsgOtRpd/UgZKTOa+sHbYJclUjkeATBqkY16Zq A==; X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="379468206" X-IronPort-AV: E=Sophos;i="6.03,165,1694761200"; d="scan'208";a="379468206" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2023 09:58:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10840"; a="817472249" X-IronPort-AV: E=Sophos;i="6.03,165,1694761200"; d="scan'208";a="817472249" Received: from dpdk-pengyuan-mev.sh.intel.com ([10.67.119.128]) by fmsmga004.fm.intel.com with ESMTP; 21 Sep 2023 09:58:48 -0700 From: "Zhang, Yuying" To: yuying.zhang@intel.com, dev@dpdk.org, qi.z.zhang@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com Subject: [PATCH v6 0/8] add rte flow support for cpfl Date: Tue, 22 Aug 2023 01:02:18 +0000 Message-Id: <20230822010226.17783-1-yuying.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230915100047.90153-1-yuying.zhang@intel.com> References: <20230915100047.90153-1-yuying.zhang@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patchset add rte flow support for cpfl driver. It depends on the following patch set: http://patchwork.dpdk.org/project/dpdk/cover/20230912173039.1612287-1-beilei.xing@intel.com/ Wenjing Qiao (2): net/cpfl: add json parser for rte flow pattern rules net/cpfl: add mod rule parser support for rte flow Yuying Zhang (6): net/cpfl: set up rte flow skeleton net/cpfl: set up control path net/cpfl: add FXP low level implementation net/cpfl: add fxp rule module net/cpfl: add fxp flow engine net/cpfl: add flow support for representor doc/guides/nics/cpfl.rst | 43 + doc/guides/rel_notes/release_23_11.rst | 1 + drivers/net/cpfl/cpfl_actions.h | 858 +++++++++++ drivers/net/cpfl/cpfl_controlq.c | 803 ++++++++++ drivers/net/cpfl/cpfl_controlq.h | 75 + drivers/net/cpfl/cpfl_ethdev.c | 392 ++++- drivers/net/cpfl/cpfl_ethdev.h | 128 ++ drivers/net/cpfl/cpfl_flow.c | 339 +++++ drivers/net/cpfl/cpfl_flow.h | 85 ++ drivers/net/cpfl/cpfl_flow_engine_fxp.c | 667 +++++++++ drivers/net/cpfl/cpfl_flow_parser.c | 1827 +++++++++++++++++++++++ drivers/net/cpfl/cpfl_flow_parser.h | 267 ++++ drivers/net/cpfl/cpfl_fxp_rule.c | 296 ++++ drivers/net/cpfl/cpfl_fxp_rule.h | 68 + drivers/net/cpfl/cpfl_representor.c | 29 + drivers/net/cpfl/cpfl_rules.c | 126 ++ drivers/net/cpfl/cpfl_rules.h | 306 ++++ drivers/net/cpfl/cpfl_vchnl.c | 144 ++ drivers/net/cpfl/meson.build | 12 + 19 files changed, 6465 insertions(+), 1 deletion(-) create mode 100644 drivers/net/cpfl/cpfl_actions.h create mode 100644 drivers/net/cpfl/cpfl_controlq.c create mode 100644 drivers/net/cpfl/cpfl_controlq.h create mode 100644 drivers/net/cpfl/cpfl_flow.c create mode 100644 drivers/net/cpfl/cpfl_flow.h create mode 100644 drivers/net/cpfl/cpfl_flow_engine_fxp.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.c create mode 100644 drivers/net/cpfl/cpfl_flow_parser.h create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.h create mode 100644 drivers/net/cpfl/cpfl_rules.c create mode 100644 drivers/net/cpfl/cpfl_rules.h