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[v2,0/3] relax io barrier for aarch64 and use smp barriers for virtual pci memory

Message ID 1576811391-19131-1-git-send-email-gavin.hu@arm.com (mailing list archive)
Headers show
Series relax io barrier for aarch64 and use smp barriers for virtual pci memory | expand


Gavin Hu Dec. 20, 2019, 3:09 a.m. UTC
Armv8's peripheral coherence order is a total order on all reads and
writes to that peripheral, that makes a compiler barrier is enough for
abstracted rte io barrier.

For virtual PCI devices, the virtual device memory is actually normal
memory and the Hypervisor view of things takes precedence and they are
within a smp configuration and smp barriers should be used, the
relaxed io barrier for aarch64 becomes insufficient.

Note for the ordering of other MMIO device memories, other than PCI,
stronger barriers might be required, which depends on the memory attributes
assigned to the memory regions. So far I did not find occurrences of such
io barriers used in non-PCI device memories within DPDK.

- remove virtio_pci_read/write64 APIs definitions, they are not needed and generate compiling errors like " error: unused function 'virtio_pci_write64' [-Werror,-Wunused-function]"
- update the reference link to kernel source code 

Gavin Hu (3):
  eal/arm64: relax the io barrier for aarch64
  net/virtio: virtual PCI requires smp barriers
  crypto/virtio: virtual PCI requires smp barriers

 drivers/crypto/virtio/virtio_pci.c                 | 108 +++++++++++++++------
 drivers/net/virtio/virtio_pci.c                    | 108 +++++++++++++++------
 .../common/include/arch/arm/rte_atomic_64.h        |   6 +-
 3 files changed, 159 insertions(+), 63 deletions(-)