From patchwork Mon Sep 16 11:27:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Hu X-Patchwork-Id: 59276 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 234BD1C0AA; Mon, 16 Sep 2019 13:27:31 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id B7C141C08E for ; Mon, 16 Sep 2019 13:27:29 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 13A851000; Mon, 16 Sep 2019 04:27:29 -0700 (PDT) Received: from net-arm-thunderx2-01.test.ast.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.40.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D53C13F59C; Mon, 16 Sep 2019 04:27:26 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, thomas@monjalon.net, bruce.richardson@intel.com, yong.liu@intel.com, yinan.wang@intel.com, ajit.khaparde@broadcom.com, somnath.kotur@broadcom.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, steve.capper@arm.com Date: Mon, 16 Sep 2019 19:27:13 +0800 Message-Id: <1568633238-47888-1-git-send-email-gavin.hu@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1567751873-15964-1-git-send-email-gavin.hu@arm.com> References: <1567751873-15964-1-git-send-email-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v2 0/5] fix and optimize barriers usage with some PMDs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" DPDK has well-defined barriers, such as CIO barriers and IO barriers. X86, as a strong ordering model, implements the barriers as compiler barriers, but on aarch64, as a weak memory ordering model, has fine grained barriers. Using correct while as relaxed as possible barriers makes a perf difference. Upon investigation on a batch of PMDs and it was found that the barriers are not always used correctly or relaxedly enough. This series of patches is to optimize the barrier usage with some selected PMDs and aim at best performance on all arches/platforms. More PMDs may come next to this series but it takes time. Gavin Hu (5): net/i40e: use relaxed and remove duplicate barrier net/ice: use relaxed and remove duplicate barrier net/bnxt: remove duplicate barrier net/bnxt: replace with cio barrier for doorbell resp net/bnxt: enforce io barrier for doorbell command drivers/net/bnxt/bnxt_hwrm.c | 11 +++++++---- drivers/net/i40e/i40e_rxtx.c | 12 +++--------- drivers/net/ice/ice_rxtx.c | 6 ------ 3 files changed, 10 insertions(+), 19 deletions(-)