From patchwork Thu Nov 19 13:57:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 84385 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 50FD0A04DD; Thu, 19 Nov 2020 14:58:08 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0093B5953; Thu, 19 Nov 2020 14:57:51 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 95BB05947 for ; Thu, 19 Nov 2020 14:57:50 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0AJDuFHJ032202 for ; Thu, 19 Nov 2020 05:57:48 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=63PN5jFId32BvD1PSSDuO4TXY+J/9w6bYkOY2JhqMdY=; b=LtThp1xsb8sqGzLAD1WbafdPEfV+AtVzxH0eALgblHKFj96xxE/1tGKBXx3XmAjI9geA tdIHIPg5dnt3z9nCGGNlMfCILjh1DURGWojQQN3gqxFkpkgXaLMrPdYpgoYmXIvfTPQT pexTxJXpPibbOXvv8iRN6A8O0QutmzARKpSArYqbIPGG36gqhOVvKpkHgqtSfLMnlWJ/ IC1d7tWHrYTz8YxrrrKHi7729kwKp3SU8LXqAJzShS3e0eHbDtEdRJ3wZCNP4ZfdjpvK zCG0YDNPeItidvpvbgYZWfzCTBizO/XdaS+bugutSkYheEKLsiRLnFd30OFau0qHDlQk qw== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 34w7ncunrj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 19 Nov 2020 05:57:48 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 Nov 2020 05:57:47 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 Nov 2020 05:57:46 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 Nov 2020 05:57:46 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.170.178]) by maili.marvell.com (Postfix) with ESMTP id 7CDD83F7040; Thu, 19 Nov 2020 05:57:44 -0800 (PST) From: To: CC: , Pavan Nikhilesh Date: Thu, 19 Nov 2020 19:27:35 +0530 Message-ID: <20201119135736.4085-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201119135736.4085-1-pbhagavatula@marvell.com> References: <20201119122336.5079-1-pbhagavatula@marvell.com> <20201119135736.4085-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-19_09:2020-11-19, 2020-11-19 signatures=0 Subject: [dpdk-dev] [PATCH v2 2/2] event/octeontx: remove selftest from dev args X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Since selftest now depends on dynamic mbuf fields it is not feasible to run selftest on device probe. Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/octeontx.rst | 12 ------------ drivers/event/octeontx/ssovf_evdev.c | 22 ++++------------------ drivers/event/octeontx/ssovf_evdev.h | 2 -- 3 files changed, 4 insertions(+), 32 deletions(-) diff --git a/doc/guides/eventdevs/octeontx.rst b/doc/guides/eventdevs/octeontx.rst index 79cae9f7d..435e1e953 100644 --- a/doc/guides/eventdevs/octeontx.rst +++ b/doc/guides/eventdevs/octeontx.rst @@ -63,18 +63,6 @@ Example: ./your_eventdev_application --vdev="event_octeontx" -Selftest --------- - -The functionality of OCTEON TX eventdev can be verified using this option, -various unit and functional tests are run to verify the sanity. -The tests are run once the vdev creation is successfully complete. - -.. code-block:: console - - --vdev="event_octeontx,selftest=1" - - Enable TIMvf stats ------------------ TIMvf stats can be enabled by using this option, by default the stats are diff --git a/drivers/event/octeontx/ssovf_evdev.c b/drivers/event/octeontx/ssovf_evdev.c index 6f242aac1..e60a7dc69 100644 --- a/drivers/event/octeontx/ssovf_evdev.c +++ b/drivers/event/octeontx/ssovf_evdev.c @@ -710,8 +710,7 @@ ssovf_close(struct rte_eventdev *dev) } static int -ssovf_selftest(const char *key __rte_unused, const char *value, - void *opaque) +ssovf_parsekv(const char *key __rte_unused, const char *value, void *opaque) { int *flag = opaque; *flag = !!atoi(value); @@ -775,10 +774,8 @@ ssovf_vdev_probe(struct rte_vdev_device *vdev) const char *name; const char *params; int ret; - int selftest = 0; static const char *const args[] = { - SSOVF_SELFTEST_ARG, TIMVF_ENABLE_STATS_ARG, NULL }; @@ -799,18 +796,9 @@ ssovf_vdev_probe(struct rte_vdev_device *vdev) "Ignoring unsupported params supplied '%s'", name); } else { - int ret = rte_kvargs_process(kvlist, - SSOVF_SELFTEST_ARG, - ssovf_selftest, &selftest); - if (ret != 0) { - ssovf_log_err("%s: Error in selftest", name); - rte_kvargs_free(kvlist); - return ret; - } - - ret = rte_kvargs_process(kvlist, - TIMVF_ENABLE_STATS_ARG, - ssovf_selftest, &timvf_enable_stats); + ret = rte_kvargs_process(kvlist, TIMVF_ENABLE_STATS_ARG, + ssovf_parsekv, + &timvf_enable_stats); if (ret != 0) { ssovf_log_err("%s: Error in timvf stats", name); rte_kvargs_free(kvlist); @@ -877,8 +865,6 @@ ssovf_vdev_probe(struct rte_vdev_device *vdev) edev->max_event_ports); ssovf_init_once = 1; - if (selftest) - test_eventdev_octeontx(); return 0; error: diff --git a/drivers/event/octeontx/ssovf_evdev.h b/drivers/event/octeontx/ssovf_evdev.h index 90d760a54..10163151c 100644 --- a/drivers/event/octeontx/ssovf_evdev.h +++ b/drivers/event/octeontx/ssovf_evdev.h @@ -86,8 +86,6 @@ #define SSO_GRP_GET_PRIORITY 0x7 #define SSO_GRP_SET_PRIORITY 0x8 -#define SSOVF_SELFTEST_ARG ("selftest") - /* * In Cavium OCTEON TX SoC, all accesses to the device registers are * implictly strongly ordered. So, The relaxed version of IO operation is