From: Tal Shnaiderman <talshn@nvidia.com>
Add a new DevX API mlx5_devx_cmd_alloc_pd() that creates a new protection
domain (PD).
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 35 ++++++++++++++++++++++++
drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++
drivers/common/mlx5/mlx5_prm.h | 36 +++++++++++++++++++++++++
drivers/common/mlx5/rte_common_mlx5_exports.def | 1 +
drivers/common/mlx5/version.map | 1 +
5 files changed, 75 insertions(+)
@@ -2002,3 +2002,38 @@ mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
invalid_buffer);
return ret;
}
+
+/*
+ * Create PD using DevX API.
+ *
+ * @param[in] ctx
+ * Context returned from mlx5 open_device() glue function.
+ *
+ * @return
+ * The DevX object created, NULL otherwise and rte_errno is set.
+ */
+struct mlx5_devx_obj *
+mlx5_devx_cmd_alloc_pd(void *ctx)
+{
+ struct mlx5_devx_obj *ppd =
+ mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
+ u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
+ u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
+
+ if (!ppd) {
+ DRV_LOG(ERR, "Failed to allocate PD data.");
+ rte_errno = ENOMEM;
+ return NULL;
+ }
+ MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
+ ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
+ out, sizeof(out));
+ if (!ppd->obj) {
+ mlx5_free(ppd);
+ DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
+ rte_errno = errno;
+ return NULL;
+ }
+ ppd->id = MLX5_GET(alloc_pd_out, out, pd);
+ return ppd;
+}
@@ -492,4 +492,6 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
__rte_internal
int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
struct mlx5_devx_virtio_q_couners_attr *attr);
+__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
#endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */
@@ -828,6 +828,8 @@ enum {
MLX5_CMD_OP_SUSPEND_QP = 0x50F,
MLX5_CMD_OP_RESUME_QP = 0x510,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
+ MLX5_CMD_OP_ALLOC_PD = 0x800,
+ MLX5_CMD_OP_DEALLOC_PD = 0x801,
MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
MLX5_CMD_OP_CREATE_TIR = 0x900,
@@ -2662,6 +2664,40 @@ struct mlx5_ifc_init2init_qp_in_bits {
u8 reserved_at_800[0x80];
};
+struct mlx5_ifc_dealloc_pd_out_bits {
+ u8 status[0x8];
+ u8 reserved_0[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_1[0x40];
+};
+
+struct mlx5_ifc_dealloc_pd_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_0[0x10];
+ u8 reserved_1[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_2[0x8];
+ u8 pd[0x18];
+ u8 reserved_3[0x20];
+};
+
+struct mlx5_ifc_alloc_pd_out_bits {
+ u8 status[0x8];
+ u8 reserved_0[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_1[0x8];
+ u8 pd[0x18];
+ u8 reserved_2[0x20];
+};
+
+struct mlx5_ifc_alloc_pd_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_0[0x10];
+ u8 reserved_1[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_2[0x40];
+};
+
#ifdef PEDANTIC
#pragma GCC diagnostic ignored "-Wpedantic"
#endif
@@ -5,6 +5,7 @@ EXPORTS
mlx5_create_mr_ext
+ mlx5_devx_cmd_alloc_pd
mlx5_devx_cmd_create_cq
mlx5_devx_cmd_create_flex_parser
mlx5_devx_cmd_create_qp
@@ -10,6 +10,7 @@ INTERNAL {
mlx5_dev_to_pci_addr;
+ mlx5_devx_cmd_alloc_pd;
mlx5_devx_cmd_create_cq;
mlx5_devx_cmd_create_flex_parser;
mlx5_devx_cmd_create_qp;