[v3,1/2] common/mlx5: add virtq attributes error fields
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Message ID 1603724687-14488-1-git-send-email-xuemingl@nvidia.com
State Superseded, archived
Delegated to: Maxime Coquelin
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  • [v3,1/2] common/mlx5: add virtq attributes error fields
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Context Check Description
ci/checkpatch success coding style OK

Commit Message

Xueming Li Oct. 26, 2020, 3:04 p.m. UTC
Add the needed fields for virtq DevX object to read the error state.

Acked-by: Matan Azrad <matan@nvidia.com>
Signed-off-by: Xueming Li <xuemingl@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++
 drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
 drivers/common/mlx5/mlx5_prm.h       | 9 +++++++--
 3 files changed, 11 insertions(+), 2 deletions(-)

Patch
diff mbox series

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 8aee12d527..dc426e9b09 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1754,6 +1754,9 @@  mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
 	attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
 					      hw_available_index);
 	attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
+	attr->state = MLX5_GET16(virtio_net_q, virtq, state);
+	attr->error_type = MLX5_GET16(virtio_net_q, virtq,
+				      virtio_q_context.error_type);
 	return ret;
 }
 
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index abbea67784..0ea2427b75 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -298,6 +298,7 @@  struct mlx5_devx_virtq_attr {
 		uint32_t size;
 		uint64_t offset;
 	} umems[3];
+	uint8_t error_type;
 };
 
 
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index d342263c85..7d671a3996 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -2280,7 +2280,8 @@  struct mlx5_ifc_virtio_q_bits {
 	u8 used_addr[0x40];
 	u8 available_addr[0x40];
 	u8 virtio_q_mkey[0x20];
-	u8 reserved_at_160[0x20];
+	u8 reserved_at_160[0x18];
+	u8 error_type[0x8];
 	u8 umem_1_id[0x20];
 	u8 umem_1_size[0x20];
 	u8 umem_1_offset[0x40];
@@ -2308,7 +2309,7 @@  struct mlx5_ifc_virtio_net_q_bits {
 	u8 vhost_log_page[0x5];
 	u8 reserved_at_90[0xc];
 	u8 state[0x4];
-	u8 error_type[0x8];
+	u8 reserved_at_a0[0x8];
 	u8 tisn_or_qpn[0x18];
 	u8 dirty_bitmap_mkey[0x20];
 	u8 dirty_bitmap_size[0x20];
@@ -2329,6 +2330,10 @@  struct mlx5_ifc_query_virtq_out_bits {
 	struct mlx5_ifc_virtio_net_q_bits virtq;
 };
 
+enum {
+	MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
+};
+
 enum {
 	MLX5_QP_ST_RC = 0x0,
 };